Hardware Acceleration of Machine Learning Beyond Linear Algebra

Sascha, Mücke,; Piatkowski, Nico; Morik, Katharina

doi:10.1007/978-3-030-43823-4_29

Cited by 6 publications

(3 citation statements)

References 5 publications

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“…These solutions allow practitioners to assess the power draw of their locally executed code directly. For inference on the edge, ML experts might also utilize devices like Raspberry Pis, ultra-low-energy hardware such as field programmable gate arrays (FPGAs) [27,28], novel memory architectures such as non-volatile memories ( [29,30]), or even hybrid architectures like quantum computers [31]. USB accelerators like the ones mentioned earlier are also specialized for inference on the edge, however still require a host system for communication.…”

Section: Related Workmentioning

confidence: 99%

Stress-Testing USB Accelerators for Efficient Edge Inference

Fischer,

Staay,

Buschjäger

2024

Preprint

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Several manufacturers sell specialized USB devices for accelerating machine learning (ML) on the edge. While being generally promoted as a versatile solution for more efficient edge inference with deep learning models, extensive practical insights on their usability and performance are hard to find. In order to make ML deployment on the edge more sustainable, our work investigates how resource efficient these USB accelerators really are. For that, we first introduce a novel and theoretically sound methodology. It allows for comparing intricate model performance in terms of quality and resource consumption across different execution environments. We then put it into practice by studying the usability and efficiency of Google's Coral edge tensor processing unit (TPU) and Intel's neural compute stick 2 (NCS). In total, we benchmark over 30 models across nine hardware configurations, which reveals intricate trade-offs. Our work demonstrates that USB accelerators are indeed capable of reducing the energy consumption by a factor up to ten, however this improvement cannot be observed for all configurations - more than 50% of the investigated models cannot be run on accelerator hardware, and in several other cases, the power draw is only marginally improved. Our experiments show that the NCS improves efficiency in a more stable way, while the TPU shows further benefits in specific cases but performs less predictable. We hope that our paper provides valuable insights for practitioners that want to deploy ML on the edge in the most efficient and sustainable way.

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Section: Related Workmentioning

confidence: 99%

Stress-Testing USB Accelerators for Efficient Edge Inference

Fischer,

Staay,

Buschjäger

2024

Preprint

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“…[11]- [13]. In lieu of a quantum computer, specialized non-quantum hardware called field-programmable gate arrays (FPGA) are also able to very quickly and energy-efficiently solve QUBO problems [14].…”

Section: Related Workmentioning

confidence: 99%

Solving Subset Sum Problems using Binary Optimization with Applications in Auditing and Financial Data Analysis

Biesner¹,

Sifa²,

Bauckhage³

2022

Preprint

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<div><br></div><div>Many applications in automated auditing and the analysis and consistency check of financial documents can be formulated in part as the subset sum problem: Given a set of numbers and a target sum, find the subset of numbers that sums up to the target. The problem is NP-hard and classical solving algorithms are therefore not practical to use in real applications. We tackle the problem as a QUBO (quadratic unconstrained binary optimization) problem and show how gradient descent on Hopfield Networks reliably finds solutions for both artificial and real data. We give an outlook for the application of specialized hardware and quantum algorithms.</div>

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“…More recently, the Ising model of quantum computation was used to evolved multiple quantum gates in simulation [13]. Similarly [18] utilized qbit encoding and the Ising model to create quantum like behaviour on FPGA-Hardware.…”

Section: Related Workmentioning

confidence: 99%

Quantum Circuit Evolution on NISQ Devices

Franken¹,

Georgiev²,

Sascha³

et al. 2020

Preprint

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Variational Quantum Eigensolvers (VQEs) have recently attracted considerable attention. Yet, in practice, they still suffer from the efforts for estimating cost function gradients for large parameter sets or resource-demanding reinforcement strategies. Here, we therefore consider recent advances in weight-agnostic learning and propose a strategy that addresses the tradeoff between finding appropriate circuit architectures and parameter tuning. We investigate the use of NEAT-inspired algorithms which evaluate circuits via genetic competition and thus circumvent issues due to exceeding numbers of parameters. Our methods are tested both via simulation and on real quantum hardware and are used to solve the transverse Ising Hamiltonian and the Sherrington-Kirkpatrick spin model.

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Hardware Acceleration of Machine Learning Beyond Linear Algebra

Cited by 6 publications

References 5 publications

Stress-Testing USB Accelerators for Efficient Edge Inference

Stress-Testing USB Accelerators for Efficient Edge Inference

Solving Subset Sum Problems using Binary Optimization with Applications in Auditing and Financial Data Analysis

Quantum Circuit Evolution on NISQ Devices

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