Hardware Acceleration of Fully Quantized BERT for Efficient Natural Language Processing

Liu, Zejian; Li, Gang; Cheng, Jian

doi:10.48550/arxiv.2103.02800

Cited by 3 publications

(5 citation statements)

References 6 publications

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“…While pruning needs balanced sparsity for high resource usage efficiency, quantization is naturally more friendly to FPGA implementations. The method in (Liu et al, 2021b) employed 8 × 4-bit and 8 × 8-bit quantization on different parts of BERT. VAQF differs from previous work in the following aspects: 1) The quantization process is guided by the compilation step that determines the required activation precision given the target frame rate; 2) The precision for activation quantization is chosen from a wider range to meet a specific real-time frame rate requirement.…”

Section: Transformer Acceleration On Fpgasmentioning

confidence: 99%

“…Our accelerators are further compared with previous work, CPU and GPU with regard to FPS, power, and energy efficiency. Since no study using quantization has been carried out for ViT acceleration on FPGAs, the accelerators for BERT in (Liu et al, 2021b) with 8 × 4-bit and 8 × 8-bit quantization are used for comparison, and other implementation results are all obtained for DeiT-base. As shown in Table 6, our W1A8 and W1A6 accelerators both outperform the BERT design on ZCU102 in terms of FPS, power and energy efficiency, and the W1A6 design has the highest FPS/W among all implementations.…”

Section: Comparison With Other Implementationsmentioning

confidence: 99%

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VAQF: Fully Automatic Software-Hardware Co-Design Framework for Low-Bit Vision Transformer

Sun¹,

Ma²,

Kang³

et al. 2022

Preprint

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The transformer architectures with attention mechanisms have obtained success in Nature Language Processing (NLP), and Vision Transformers (ViTs) have recently extended the application domains to various vision tasks. While achieving high performance, ViTs suffer from large model size and high computation complexity that hinders the deployment of them on edge devices. To achieve high throughput on hardware and preserve the model accuracy simultaneously, we propose VAQF, a framework that builds inference accelerators on FPGA platforms for quantized ViTs with binary weights and low-precision activations. Given the model structure and the desired frame rate, VAQF will automatically output the required quantization precision for activations as well as the optimized parameter settings of the accelerator that fulfill the hardware requirements. The implementations are developed with Vivado High-Level Synthesis (HLS) on the Xilinx ZCU102 FPGA board, and the evaluation results with the DeiT-base model indicate that a frame rate requirement of 24 frames per second (FPS) is satisfied with 8-bit activation quantization, and a target of 30 FPS is met with 6-bit activation quantization. To the best of our knowledge, this is the first time quantization has been incorporated into ViT acceleration on FPGAs with the help of a fully automatic framework to guide the quantization strategy on the software side and the accelerator implementations on the hardware side given the target frame rate. Very small compilation time cost is incurred compared with quantization training, and the generated accelerators show the capability of achieving real-time execution for state-of-the-art ViT models on FPGAs.

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Section: Transformer Acceleration On Fpgasmentioning

confidence: 99%

Section: Comparison With Other Implementationsmentioning

confidence: 99%

VAQF: Fully Automatic Software-Hardware Co-Design Framework for Low-Bit Vision Transformer

Sun¹,

Ma²,

Kang³

et al. 2022

Preprint

View full text Add to dashboard Cite

show abstract

“…In many edge devices, computational resources are minimal (Liu, Li, and Cheng 2021). It is not easy to run two large parameter models simultaneously, which leads to the necessity of releasing the resources of the old model to reload the new model when switching tasks, a process we call redeployment.…”

Section: The Efficiency Of Plug-taggermentioning

confidence: 99%

Plug-Tagger: A Pluggable Sequence Labeling Framework Using Language Models

Zhou,

Ma,

Gui

et al. 2021

Preprint

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Plug-and-play functionality allows deep learning models to adapt well to different tasks without requiring any parameters modified. Recently, prefix-tuning was shown to be a plugand-play method on various text generation tasks by simply inserting corresponding continuous vectors into the inputs. However, sequence labeling tasks invalidate existing plugand-play methods since different label sets demand changes to the architecture of the model classifier. In this work, we propose the use of label word prediction instead of classification to totally reuse the architecture of pre-trained models for sequence labeling tasks. Specifically, for each task, a label word set is first constructed by selecting a high-frequency word for each class respectively, and then, task-specific vectors are inserted into the inputs and optimized to manipulate the model predictions towards the corresponding label words. As a result, by simply switching the plugin vectors on the input, a frozen pre-trained language model is allowed to perform different tasks. Experimental results on three sequence labeling tasks show that the performance of the proposed method can achieve comparable performance with standard fine-tuning with only 0.1% taskspecific parameters. In addition, our method is up to 70 times faster than non-plug-and-play methods while switching different tasks under the resource-constrained scenario.

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“…For non-linear functions such as Softmax and LayerNorm, it analyses and designs detailed computational flows and hardware structures. [16] investigates the acceleration of BERT on FPGAs. To reduce the memory footprint, the authors fully quantize all parameters of BERT, including weights, activations, scale factors, SoftMax, layer normalization and other intermediate results.…”

Section: Customized Acceleratorsmentioning

confidence: 99%

“…In comparison experiments with other works based on reconfigurable device, to our knowledge, no researcher has applied Transformer-based visual models to the field of reconfigurable computation, so this paper compares our design to other Transformer model in the NLP. FQ-BERT is a fully quantized Bert proposed by [16]. The 8-bit NPE of NVU-1024 [23] is an overlay processor for BERT-based models.…”

Section: Comparison With Cpu Gpu Fpgamentioning

confidence: 99%

Vis-TOP: Visual Transformer Overlay Processor

Hu¹,

Xu²,

Fan³

et al. 2021

Preprint

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In recent years, Transformer [23] has achieved good results in Natural Language Processing (NLP) and has also started to expand into Computer Vision (CV). Excellent models such as the Vision Transformer [5] and Swin Transformer [17] have emerged. At the same time, the platform for Transformer models was extended to embedded devices to meet some resource-sensitive application scenarios. However, due to the large number of parameters, the complex computational flow and the many different structural variants of Transformer models, there are a number of issues that need to be addressed in its hardware design. This is both an opportunity and a challenge. We propose Vis-TOP (Visual Transformer Overlay Processor), an overlay processor for various visual Transformer models. It differs from coarse-grained overlay processors such as CPU, GPU, NPE, and from fine-grained customized designs for a specific model. Vis-TOP summarizes the characteristics of all visual Transformer models and implements a three-layer and two-level transformation structure that allows the model to be switched or changed freely without changing the hardware architecture. At the same time, the corresponding instruction bundle and hardware architecture are designed in three-layer and two-level transformation structure. After quantization of Swin Transformer tiny model using 8-bit fixed points (fix_8), we implemented an overlay processor on the ZCU102. Compared to GPU, the TOP throughput is 1.5x higher. Compared to the existing Transformer accelerators, our throughput per DSP is between 2.2x and 11.7x higher than others. In a word, the approach in this paper meets the requirements of real-time AI in terms of both resource consumption and inference speed. Vis-TOP provides a cost-effective and power-effective solution based on reconfigurable devices for computer vision at the edge.

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Hardware Acceleration of Fully Quantized BERT for Efficient Natural Language Processing

Cited by 3 publications

References 6 publications

VAQF: Fully Automatic Software-Hardware Co-Design Framework for Low-Bit Vision Transformer

VAQF: Fully Automatic Software-Hardware Co-Design Framework for Low-Bit Vision Transformer

Plug-Tagger: A Pluggable Sequence Labeling Framework Using Language Models

Vis-TOP: Visual Transformer Overlay Processor

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