HAPE: A high-level area-power estimation framework for FPGA-based accelerators

Makni, Mariem; Niar, Smaïl; Baklouti, Mouna; Abid, Mohamed

doi:10.1016/j.micpro.2018.08.004

Cited by 14 publications

(14 citation statements)

References 3 publications

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“…The employed power model directly derives the power consumption from the estimated resource usage of the system in an approach similar to HAPE [18]. To account for error propagation in quality assessment, a software simulation is used together with a user selectable metric which is evaluated over a training data set.…”

Section: Methodsmentioning

confidence: 99%

Region of Interest-Based Parameter Optimization for Approximate Image Processing on FPGAs

Manuel

Kreddig²,

Conrady

et al. 2021

IJNC

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In recent years, technological advancements in computer hardware systems have been lagging behind the demand for increased computational power, especially in application domains such as signal and image processing. Approximate computing is a design paradigm for efficient system design to overcome this bottleneck by exploiting the resilience of such applications to inaccuracy in their computations and trading off quality for hardware resource savings. Over the years, many approximation techniques have been proposed on various abstraction layers and demonstrated their effectiveness in different applications. Combining multiple methods in a larger system can further increase the resulting benefits. However, this often leads to a non-trivial optimization task of finding the best parameterization across all employed methods. The interaction and influence of error propagation between individual components demand a global optimization of parameters that simultaneously considers all the parameters for each of the approximation techniques used. In this work, we propose a methodology for exploring such highly complex design spaces using a multi-objective genetic algorithm in an FPGA-based system. Simple models are used for the estimation of resource demands in terms of power together with the anticipated quality degradation. The optimization is carried out to determine the trade-off between these objectives. We demonstrate the effectiveness of our approach on a typical color processing pipeline by tailoring the encoding and genetic operations to the needs of this application. To focus the optimization into a relevant region of interest, we propose ROI-NSGA, a novel variant of nondominated solution selection, and compare its optimization efficiency with the traditional NSGA-II approach for the examined case study. Our results show that the models are able to guide the optimization, and that the genetic operations and selections are capable to find Pareto-optimal solutions, among which the desired quality-resource trade-off can be chosen. Besides, the ROI-NSGA based optimization outperforms the results obtained for the case study using the NSGA-II approach within the region of interest.

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Section: Methodsmentioning

confidence: 99%

Region of Interest-Based Parameter Optimization for Approximate Image Processing on FPGAs

Manuel

Kreddig²,

Conrady

et al. 2021

IJNC

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“…Due to various factors, there is heterogeneity in the dynamic power of chips for Fin-FET-based microprocessors [ 8 ]. A high-level area and power estimator, based on analytical modeling is proposed in [ 9 ]. It helps designers to have an early estimate of the power and area of FPGA-based accelerators.…”

Section: Literature Reviewmentioning

confidence: 99%

Efficient power macromodeling approach for heterogeneously stacked 3d ICs using Bio-geography based optimization

Siddiq

Durrani

2022

PLoS ONE

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Low-power consumption has been always a crucial design constraint for an efficient intellectual property based three-dimensional multi-core system that cannot be ignored easily. As the complexity increases due to the number of cores/stacks/ layers in 3D digital systems, the challenges to handle power can be more difficult at a high abstraction level. Therefore, the low-power approach gives designers an opportunity to estimate and optimize the power consumption in the early stages of design phases. The accurate power estimation through the macro-modeling approach at high-level reduces the risk of redesign cycle and turn-around time. In this research, we have presented an improved statistical macro-modeling approach that estimates power through statistical characteristics of randomly generated input patterns by using Biogeography Based Optimization. These input patterns propagate signals into an IP-based 3D digital test system. In experiments, the test system is based on four 8 to 32- bits heterogeneous cores. The response of the power is monitored by applying the well-known Monte Carlo Simulation technique. The entire power estimation method is performed in two major steps. First, the average power is estimated for an IP-based individual core. Second, the average power for bus-based Through-Silicon-Via is estimated. Finally, the cores and B-TSVs are integrated together to construct a 3D system. Then the average power for complete test systems is estimated. The experimental results of the statistical power macro-model are compared with the commercial Electronic Design Automation power simulator at the operating frequency of 100 MHz. The average percentage error of the test system is calculated as 8.65%. For the validation of these results, the statistical error analysis is additionally performed and reveals that our proposed macro-model is accurate in terms of percentage of error with a feasible amount of time.

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“…As complexity of hardware systems is growing, a solution could be to automatically identify signals that are the main contributor to power consumption and guide power estimation tools [85], [86]. Another solution could be to directly make use of High-level Synthesis to create power models based on resource utilization and real measurements, in order to explore impact of HLS directives on both power and area [87].…”

Section: Polynomial-based Power Modelsmentioning

confidence: 99%

RTL to Transistor Level Power Modeling and Estimation Techniques for FPGA and ASIC: A Survey

Nasser

Lorandel

Prévotet

et al. 2021

IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst.

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Power consumption constitutes a major challenge for electronics circuits. One possible way to deal with this issue is to consider it very soon in the design process in order to explore various design choices. A typical design flow often starts with a high-level description of a full system, which imposes to provide accurate models. Power modelling techniques can be employed, providing a way to find a relationship between power and other metrics. Furthermore, it is also important to consider efficient power characterization techniques. The role of this paper is, first, to provide an overview of RTL to transistor level power modelling and estimation techniques for FPGAs and ASICs devices. Second, it aims at proposing a classification of all approaches according to defined metrics, which should help designers in finding a particular method for their specific situation, even if no common reference is defined among the considered works. Index Terms-Power consumption, power modelling, power estimation, high-level power estimation, FPGA, ASIC, tools.. Antifuse Technology (e.g., Actel TM , Quicklogic TM): an antifuse remains in a high-impedance state until it is programmed into a low-impedance or "fused" state (Figure 9.18). This technology can be used only once on one-time programmable (OTP) devices; it is less expensive than the RAM technology.

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HAPE: A high-level area-power estimation framework for FPGA-based accelerators

Cited by 14 publications

References 3 publications

Region of Interest-Based Parameter Optimization for Approximate Image Processing on FPGAs

Region of Interest-Based Parameter Optimization for Approximate Image Processing on FPGAs

Efficient power macromodeling approach for heterogeneously stacked 3d ICs using Bio-geography based optimization

RTL to Transistor Level Power Modeling and Estimation Techniques for FPGA and ASIC: A Survey

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