Guaranteed bandwidth using looped containers in temporally disjoint networks within the nostrum network on chip

Millberg, Mikael; Nilsson, Erland; Thid, Rikard; Jantsch, Axel

doi:10.1109/date.2004.1269001

Cited by 243 publications

(193 citation statements)

References 10 publications

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“…Some other important concepts in NOC are topology, routing, flow control, buffer management, quality of service and network interfaces and they have been studied in acclaimed proposals such as Aetherial [9], Nostrum [10], Xpipes [11], Intel 80 Core NOC [12], and Mango [13]. They all make different design decisions, to achieve their design goals.…”

Section: B Network-on-chipmentioning

confidence: 99%

Hardware design and implementation of a Network-on-Chip based load balancing switch fabric

Karadeniz

Mhamdi

Goossens

et al. 2012

2012 International Conference on Reconfigurable Computing and FPGAs

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Abstract-Network routers rely on an important hardware component, namely the switch fabric, responsible for forwarding incoming packets to their respective output ports according to a scheduling algorithm. A switch fabric mainly consists of buffering memories for temporary queuing and the scheduling unit(s) for forwarding.In this paper, we revisit our previously proposed Networkon-Chip (NOC) based switch fabric architecture and: 1) propose an FPGA based hardware implementation of the NOC switch; 2) carry out performance tests, both via RTL simulations and actual execution on FPGA, under uniform traffic flows; and 3) present results in terms of throughput, average latency, and average bitrate. Our results show that our architecture i) performs as good as other buffering schemes/scheduling algorithms that theoretically achieve 100% throughput, ii) is at least as scalable as other architectures in terms of hardware cost, iii) is perfectly implementable and iv) introduces NOC concepts, which have originally been borrowed from computer networks, back into computer networks.

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Section: B Network-on-chipmentioning

confidence: 99%

Hardware design and implementation of a Network-on-Chip based load balancing switch fabric

Karadeniz

Mhamdi

Goossens

et al. 2012

2012 International Conference on Reconfigurable Computing and FPGAs

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“…Specifically, the connection path between the source and destination pair of GS packets is built at the time before they are injected onto the network [44][45][46][47][48][49][50][51]. However, this kind of static preallocation may result in high service latency and does not consider hotspots created by temporal shifts in data requirements, thus, leads to a rather unscalable NoC.…”

Section: Connection-oriented Schemementioning

confidence: 99%

Networks on Chips: Structure and Design Methodologies

Tsai

Lan

et al. 2011

Journal of Electrical and Computer Engineering

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The next generation of multiprocessor system on chip (MPSoC) and chip multiprocessors (CMPs) will contain hundreds or thousands of cores. Such a many-core system requires high-performance interconnections to transfer data among the cores on the chip. Traditional system components interface with the interconnection backbone via a bus interface. This interconnection backbone can be an on-chip bus or multilayer bus architecture. With the advent of many-core architectures, the bus architecture becomes the performance bottleneck of the on-chip interconnection framework. In contrast, network on chip (NoC) becomes a promising on-chip communication infrastructure, which is commonly considered as an aggressive long-term approach for onchip communications. Accordingly, this paper first discusses several common architectures and prevalent techniques that can deal well with the design issues of communication performance, power consumption, signal integrity, and system scalability in an NoC. Finally, a novel bidirectional NoC (BiNoC) architecture with a dynamically self-reconfigurable bidirectional channel is proposed to break the conventional performance bottleneck caused by bandwidth restriction in conventional NoCs.

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“…For this purpose we use the platform template described in [11]. The platform template uses a tile based hardware architecture, with tiles connected using a predictable hardware interconnect, such as those described in [17]- [19]. The platform implementation that we use for experimentation follows this template using the AEthereal Network-on-Chip (NoC) [17] to connect a configurable number of Xilinx [20] MicroBlaze (µBlaze) processor based tiles, as illustrated in Figure 3.…”

Section: Introductionmentioning

confidence: 99%

Power Minimisation for Real-Time Dataflow Applications

Nelson

Moreira

Molnos

et al. 2011

2011 14th Euromicro Conference on Digital System Design

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Abstract-Energy efficient execution of applications is important for many reasons, e.g. time between battery charges, device temperature. Voltage and Frequency Scaling (VFS) enables applications to be run at lower frequencies on hardware resources thereby consuming less power. Real-time applications have deadlines that must be met otherwise their output is devalued. Dataflow modelling of real-time applications enables off-line verification of the application's temporal requirements. In this paper we describe a method to reduce the combined static and dynamic energy consumption using a Dynamic VFS (DVFS) technique for dataflow modelled real-time applications that may be mapped onto multiple hardware resources. We achieve this by using an application's static slack in order to perform DVFS while still satisfying the application's temporal requirements. We show that by formulating a dataflow modelled application and its mapping as a convex optimisation problem, with energy consumption as the objective function, the problem can be solved with a generic convex optimisation solver, producing an energyoptimal constant frequency per application task. Our method allows task frequencies to be constrained such that, e.g. one frequency per application or per processor may be achieved.

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Guaranteed bandwidth using looped containers in temporally disjoint networks within the nostrum network on chip

Cited by 243 publications

References 10 publications

Hardware design and implementation of a Network-on-Chip based load balancing switch fabric

Hardware design and implementation of a Network-on-Chip based load balancing switch fabric

Networks on Chips: Structure and Design Methodologies

Power Minimisation for Real-Time Dataflow Applications

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