Growth and Selective Etch of Phosphorus-Doped Silicon/Silicon–Germanium Multilayers Structures for Vertical Transistors Application

Abstract

Vertical gate-all-around field-effect transistors (vGAAFETs) are considered as the potential candidates to replace FinFETs for advanced integrated circuit manufacturing technology at/beyond 3-nm technology node. A multilayer (ML) of Si/SiGe/Si is commonly grown and processed to form vertical transistors. In this work, the P-incorporation in Si/SiGe/Si and vertical etching of these MLs followed by selective etching SiGe in lateral direction to form structures for vGAAFET have been studied. Several strategies were proposed for the epitaxy such as hydrogen purging to deplete the access of P atoms on Si surface, and/or inserting a Si or Si0.93Ge0.07 spacers on both sides of P-doped Si layers, and substituting SiH4 by SiH2Cl2 (DCS). Experimental results showed that the segregation and auto-doping could also be relieved by adding 7% Ge to P-doped Si. The structure had good lattice quality and almost had no strain relaxation. The selective etching between P-doped Si (or P-doped Si0.93Ge0.07) and SiGe was also discussed by using wet and dry etching. The performance and selectivity of different etching methods were also compared. This paper provides knowledge of how to deal with the challenges or difficulties of epitaxy and etching of n-type layers in vertical GAAFETs structure.

First Demonstration of Novel Vertical Gate-All-Around Field-Effect-Transistors Featured by Self-Aligned and Replaced High-κ Metal Gates

“…17 However, a serious problem was found due to the segregation of n-type dopants, and this phenomenon is very common. 18 It causes great performance loss, or very harsh control toward the diameters of NWs to reach depletion (less than 6 nm) according to our work. A similar conclusion was also found in other research.…”

“…For better effective-gate-length control and less variation, epitaxially grown channel materials with in situ doped S/Ds, and self-aligned gates, are introduced in our previous work . However, a serious problem was found due to the segregation of n-type dopants, and this phenomenon is very common . It causes great performance loss, or very harsh control toward the diameters of NWs to reach depletion (less than 6 nm) according to our work.…”

CMOS Scaling for the 5 nm Node and Beyond: Device, Process and Technology

“…In terms of process, both Si and SiGe can be used as the channel, which depends on the structure of the Si/Ge thin film material and the etching process [197][198][199]. It is worth mentioning that if you want to use SiGe as the sacrificial layer and Si as the channel, then epitaxial growth of low Ge components is recommended, as this avoids creating defects during the growth process.…”

Interface Investigation on SiGe/Si Multilayer Structures: Influence of Different Epitaxial Process Conditions

“…compatibility. Compared to the high-vacuum MBE reaction with a clean dangling bond surface, the CVD reaction process is more complex, and the material surface is generally rich in reaction byproducts and precursor molecules. ,,− For the SiGe/Si MLs structure, in the process of growing SiGe on the Si layer, the Si–SiGe interface tends to be abrupt. However, during Si deposition on SiGe layers, the dangling bond energy causes that deposited Si to diffuse into the subsurface layers, forming a broad interface. ,,− In previous studies, the introduction of surfactants to passivate the dangling bonds on Si/Ge surfaces can effectively improve the interface characterization.…”