2008
DOI: 10.1016/j.ijmachtools.2008.05.009
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Grinding of silicon wafers: A review from historical perspectives

Abstract: The majority of semiconductor devices are built on silicon wafers. Manufacturing of high quality silicon wafers involves several machining processes including grinding. This review paper discusses historical perspectives on grinding of silicon wafers, impacts of wafer size progression on applications of grinding in silicon wafer manufacturing, and interrelationships between grinding and two other silicon machining processes (slicing and polishing). It is intended to help * Corresponding author. Tel.: +1 785 53… Show more

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Cited by 151 publications
(51 citation statements)
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References 32 publications
(43 reference statements)
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“…Furthermore, the abrasive processes will cause surface flatness deviation due to its uncontrollable material removal resulting in the machined profile inaccuracy [2]. Therefore, after grinding and lapping processes, the chemical-mechanical polishing (CMP) is essential to remove the subsurface damage layer caused by the hard abrasive particles, which makes a very costly production [3]. Also, these abrasive processes especially like CMP are extremely slow, whiles grinding and lapping processes would impart subsurface damage leading to a degraded surface integrity [4].…”
Section: Introductionmentioning
confidence: 99%
“…Furthermore, the abrasive processes will cause surface flatness deviation due to its uncontrollable material removal resulting in the machined profile inaccuracy [2]. Therefore, after grinding and lapping processes, the chemical-mechanical polishing (CMP) is essential to remove the subsurface damage layer caused by the hard abrasive particles, which makes a very costly production [3]. Also, these abrasive processes especially like CMP are extremely slow, whiles grinding and lapping processes would impart subsurface damage leading to a degraded surface integrity [4].…”
Section: Introductionmentioning
confidence: 99%
“…The thinned wafers are transferred using a carrier wafer, following which the thin membrane is eventually removed. [112] In addition, thin Si-based devices and nanomembranes can also be achieved by chemical etching of SOI (Si on Insulator) wafer. Chemical etching of Si can be achieved either via both dry and wet etching process.…”
Section: Ultra-thin Silicon Chipsmentioning
confidence: 99%
“…Although well accepted in silicon wafer foundry, CMP has extremely low efficiency on material removal, the CMP solution can cause pollution to environment, and the process is difficulty to be automated [9,10]. Those disadvantages become more severe with the increased wafer size [11,12]. Therefore, it is necessary to develop new surface planarization process, which could overcome those drawbacks.…”
Section: Introductionmentioning
confidence: 99%