Gridded design rule scaling: taking the CPU toward the 16nm node

Abstract

The Intel 45nm Penryn™ CPU was a landmark design, not only for its implementation of high-K metal gate materials 1 , but also for the adoption of a nearly gridded design rule (GDR) layout architecture for the poly silicon gate layer 2 . One key advantage of using gridded design rules is reduction of design rules and ease of 1-dimensional scaling compared to complex random 2-dimensional layouts. In this paper, we demonstrate the scaling capability of GDR to 16nm and 22nm logic nodes. Copying the design of published images for the Intel 45nm Penryn™ poly-silicon layer 2 , we created a mask set designed to duplicate those patterns targeting a final pitch of 64nm and 52nm using Sidewall Spacer Double Patterning for the extreme pitch shrinking and performed exploratory work at final pitch of 44nm. Mask sets were made in both tones to enable demonstration of both damascene (dark field) patterning and poly-silicon gate layer (clear field) GDR layouts, although the results discussed focus primarily on poly-silicon gate layer scaling.The paper discusses the line-and-cut double patterning technique for generating GDR structures, the use of sidewall spacer double patterning for scaling parallel lines and the lithographic process window (CD and alignment) for applying cut masks. Through the demonstration, we highlight process margin issues and suggest corrective actions to be implemented in future demonstrations and more advanced studies. Overall, the process window is quite large and the technique has strong manufacturing possibilities.

N³ASICs: Designing nanofabrics with fine-grained CMOS integration

“…al. [7] project that the metal 1(M1) pitch for the 16nm technology node is 40nm. This is equal to 5λ where λ=8nm for 16nm technology node.…”

“…The interconnects were modeled using the Predictive Technology Model (PTM) [2] [40] models. The dimensions and parameters for scaled CMOS interconnect were chosen as projected by ITRS [1] and [7]. With the help of …”

“…PTM interconnects models were used to obtain the RC value of interconnects. The parameters chosen for the interconnects were in accordance with ITRS and [7].…”

Low-Power Heterogeneous Graphene Nanoribbon-CMOS Multistate Volatile Memory Circuit

“…PTM interconnect RC models based on scaled interconnect dimensions were used in conjunction with the PTM transistor models for power and performance evaluation of GNTRAM using HSPICE. For physical layout design and area evaluation of GNTRAM, 1-D gridded design rules [Bencher et al 2009] were used as shown in Table II. For benchmarking against CMOS, 16nm Gridded 8T SRAM cell [Greenway et al 2008] was used, since this SRAM design utilizes the same grid-based design used in GNTRAM. Regular 6T CMOS SRAM scaled to 16nm technology node was also used for benchmarking.…”

Extending SMO into the lens pupil domain

“…Aerial images were calculated in order to evaluate the impact of the mask topography without the effect of photoresist. 1D mask layouts were used in order to conform to the gridded design layouts currently used by industry [12]. The mask was an unbiased dual trench (π/3π) alternating phase shift mask (AltPSM) of chromium oxide on quartz, with etch depths of 85.7/257.1 nm, duty ratio of 1:1, and a pitch of 90, 100, or 110 nm.…”