Grenoble Large Scale Facilities for Advanced Characterisation of Microelectronics Devices

Beaucour, J.; Segura-Ruíz, Jaime; Giroud, Benjamin; Capria, Ennio; Mitchell, Edward P.; Curfs, C.; Royer, Jean‐Claude; Baylac, M.; Villa, Francesca; Rey, Solenne

doi:10.1109/radecs.2015.7365616

Cited by 23 publications

(16 citation statements)

References 1 publication

Supporting

Mentioning

Contrasting

Order By: Relevance

“…Two commercial 2M×8-bit CMOS SRAMs, the CY62167DV and CY62167EV, from Cypress Semiconductor and in 130 & 90 nm technologies respectively, were irradiated in the 14-MeV neutron source GENEPI2, available at the LPSC (Laboratoire de Physique Subatomique et de Cosmologie), in Grenoble (France) [9], [10]. SRAMs were set at a fairly large distance from the target (40 cm), to limit the neutron flux to approximately 3 × 10 4 n·cm −2 ·s −1 .…”

Section: Methodsmentioning

confidence: 99%

“…In other words, the existence of a theoretical model provides a well-founded reason to find the values that, probably, link addresses involved in one multiple event. We have validated this approach with experimental data issued from experiments on commercial Cypress SRAMs with 14-MeV neutrons, in the GENEPI2 neutron source (GEnérateur à NEutrons Pulsés Intenses) [9], [10]. The different cross-sections issued from these experiments were used to predict the theoretical soft error rate of the memories, which was compared with experimental values obtained in high altitude environments.…”

mentioning

confidence: 95%

“…The main difference is that it processes the values that appear too frequently after XORing (instead of subtracting) the addresses with bitflips, as it was sketched in previous works [9]. The main advantage being that it is possible to accurately predict the expected frequency of values in a system where only SBUs occur and to compare the predictions with the actual data.…”

mentioning

confidence: 99%

See 2 more Smart Citations

Statistical Anomalies of Bitflips in SRAMs to Discriminate SBUs From MCUs

Clemente

Franco

Villa

et al. 2016

IEEE Trans. Nucl. Sci.

View full text Add to dashboard Cite

Abstract-Recently, the occurrence of multiple events in static tests has been investigated by checking the statistical distribution of the difference between the addresses of the words containing bitflips. That method has been successfully applied to Field Programmable Gate Arrays (FPGAs) and the original authors indicate that it is also valid for SRAMs. This paper presents a modified methodology that is based on checking the XORed addresses with bitflips, rather than on the difference. Irradiation tests on CMOS 130 & 90 nm SRAMs with 14-MeV neutrons have been performed to validate this methodology. Results in high-altitude environments are also presented and cross-checked with theoretical predictions. In addition, this methodology has also been used to detect modifications in the organization of said memories. Theoretical predictions have been validated with actual data provided by the manufacturer.

show abstract

Section: Methodsmentioning

confidence: 99%

mentioning

confidence: 95%

mentioning

confidence: 99%

See 1 more Smart Citation

Statistical Anomalies of Bitflips in SRAMs to Discriminate SBUs From MCUs

Clemente

Franco

Villa

et al. 2016

IEEE Trans. Nucl. Sci.

View full text Add to dashboard Cite

show abstract

“…The GEnerator of NEutrons Pulsed and Intense (GENEPI2) is under operation at LPSC (Laboratoire de Physique Subatomique et de Cosmologie) in Grenoble (France) [12], [13]. This accelerator, originally developed to produce neutrons for nuclear physics experiments, was used for the first time in 2013 to irradiate different types of SRAMs.…”

Section: A Description Of the Genepi2 Neutron Sourcementioning

confidence: 99%

Single Events in a COTS Soft-Error Free SRAM at Low Bias Voltage Induced by 15-MeV Neutrons

Clemente

Franco

Villa

et al. 2016

IEEE Trans. Nucl. Sci.

View full text Add to dashboard Cite

This paper presents an experimental study of the sensitivity to 15-MeV neutrons of Advanced Low Power SRAMs (A-LPSRAM) at low bias voltage little above the threshold value that allows the retention of data. This family of memories is characterized by a 3D structure to minimize the area penalty and to cope with latchups, as well as by the presence of integrated capacitors to hinder the occurrence of single event upsets. In low voltage static tests, classical single event upsets were a minor source of errors, but other unexpected phenomena such as clusters of bitflips and hard errors turned out to be the origin of hundreds of bitflips. Besides, errors were not observed in dynamic tests at nominal voltage. This behavior is clearly different than that of standard bulk CMOS SRAMs, where thousands of errors have been reported.

show abstract

“…In other words, the existence of a theoretical model provides a well-founded reason to find the values that, probably, link addresses involved in one multiple event. We have validated this approach with experimental data issued from experiments in commercial Cypress SRAM memories with 15 MeV neutrons, in the GENEPI2 neutron source [3], [4]. Data obtained in high-altitude environments have been included in the full length paper sent to IEEE Tran.…”

mentioning

confidence: 99%