Graphoepitaxial and chemoepitaxial methods for creating line-space patterns at 33nm pitch: comparison to a HVM process

Millward, Dan B.; Lugani, Gurpreet S.; Light, Scott; Niroomand, Ardavan; Hustad, Phillip D.; Trefonas, Peter; Quach, Dung; Ginzburg, Valeriy V.

doi:10.1117/12.2086693

Cited by 5 publications

(2 citation statements)

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“…It has been shown that DSA patterns can achieve density multiplication with respect to the guiding pattern [178][179][180][181][182], and that templates can enforce complex local patterns [183,184] using minimal design rules [180,185]. Progressively more complex integration of BCPs into realistic industrial microelectronic workflows has been demonstrated [39,183,[186][187][188][189][190][191]. BCPs may thus play a role in future electronics and memory devices (resistive [192,193], phasechange [194,195], or magnetic bit-patterned media [137,196,197]).…”

Section: Introductionmentioning

confidence: 99%

Rapid ordering of block copolymer thin films

Majewski

Yager

2016

J. Phys.: Condens. Matter

156

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Block-copolymers self-assemble into diverse morphologies, where nanoscale order can be finely tuned via block architecture and processing conditions. However, the ultimate usage of these materials in real-world applications may be hampered by the extremely long thermal annealing times-hours or days-required to achieve good order. Here, we provide an overview of the fundamentals of block-copolymer self-assembly kinetics, and review the techniques that have been demonstrated to influence, and enhance, these ordering kinetics. We discuss the inherent tradeoffs between oven annealing, solvent annealing, microwave annealing, zone annealing, and other directed self-assembly methods; including an assessment of spatial and temporal characteristics. We also review both real-space and reciprocal-space analysis techniques for quantifying order in these systems.

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Section: Introductionmentioning

confidence: 99%

Rapid ordering of block copolymer thin films

Majewski

Yager

2016

J. Phys.: Condens. Matter

156

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“…Double patterning is one such process. 26 Directed selfassembly also shows potential for enabling use of much faster resists. (A paper was presented at the SPIE Microlithography Conference of 2020, "Enabling Moore's law with DSA," by G. Singh, E. Han, and F. Gstrein.…”

Section: Stochasticsmentioning

confidence: 99%

International Roadmap for Devices and Systems lithography roadmap

Neisser

2021

J. Micro/Nanopattern. Mats. Metro.

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Background: Planned improvements in semiconductor chip performance have historically driven improvements in lithography and this is expected to continue in the future. The International Roadmap for Devices and Systems roadmap helps the industry plan for the future. Aim:The 2021 lithography roadmap shows requirements, possible options, and challenges for the next 15 years.Results: Critical dimensions in logic chips are now small enough that stochastics, i.e., random variations in photon, molecules, and photoresist image forming processes, introduces random variations in sizes and stochastic-driven defects. As critical dimensions get smaller, stochastics becomes a bigger challenge. The roadmap projects that despite projected improvements in tools, photoresist, device design, and patterning processes, resist dose to print will still have to roughly triple over the next 10 years to maintain acceptable stochastics unless major process or chip design changes are made. This will raise patterning costs substantially. Other patterning options are under development but they also have challenges related to defects. Edge placement error (EPE) is also a challenge for future devices. Long-term, logic device requirements will drive stacked devices, and yield and process complexity will be key challenges.Conclusions: Logic devices will drive leading edge lithography. Improved extreme ultraviolet lithography is a leading candidate but other options are possible. Key short-term challenges are stochastics, EPE, and cost. Resist dose to print is expected to rise substantially as critical dimensions shrink unless substantial process innovation occurs. For the long term, the challenges will be yield and process complexity when logic devices switch to 3D scaling

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