GraphABCD: Scaling Out Graph Analytics with Asynchronous Block Coordinate Descent

Yang, Yifan; Li, Zhaoshi; Deng, Yangdong; Liu, Zhiwei; Yin, Shouyi; Wei, Shaojun; Liu, Leibo

doi:10.1109/isca45697.2020.00043

Cited by 22 publications

(3 citation statements)

References 47 publications

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“…However, they only cover SM-GNN instead of the multi-node LSD-GNN we target in this paper. Graph analysis hardware: There are also works on customized hardware for graph analytics, including ASIC [13,17,30,46,57,70,71], FPGA/GPU [18,19,50,67,73], and processing customizations [10,72]. However, these works are not well associated with GNN applications nor limited on focusing the single machine cases.…”

Section: Related Workmentioning

confidence: 99%

Hyperscale FPGA-as-a-service architecture for large-scale distributed graph neural network

Niu

Wang

et al. 2022

Proceedings of the 49th Annual International Symposium on Computer Architecture

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Graph neural network (GNN) is a promising emerging application for link prediction, recommendation, etc. Existing hardware innovation is limited to single-machine GNN (SM-GNN), however, the enterprises usually adopt huge graph with large-scale distributed GNN (LSD-GNN) that has to be carried out with distributed inmemory storage. The LSD-GNN is very different from SM-GNN in terms of system architecture demand, workflow and operators, and hence characterizations.In this paper, we first quantitively characterize the LSD-GNN with industrial-grade framework and application, summarize that its challenges lie in graph sampling, including distributed graph access, long latency, and underutilized communication and memory bandwidth. These challenges are missing from previous SM-GNN targeted researches. We then propose a customized hardware architecture to solve the challenges, including a fully pipelined access engine architecture for graph access and sampling, a low-latency and bandwidth-efficient customized memory-over-fabric hardware, and a RISC-V centric control system providing good programmability. We implement the proposed architecture with full software support in a 4-card FPGA heterogeneous proof-of-concept (PoC) system. Based on the measurement result from the FPGA PoC, we demonstrate a single FPGA can provide up to 894 vCPU's sampling capability. With the goal of being profitable, programmable, and scalable, we further integrate the architecture to FPGA cloud (FaaS) at hyperscale, along with the industrial software framework. We explicitly explore eight FaaS architectures that carry out the proposed accelerator hardware. We finally conclude that off-the-shelf FaaS.base can already provide 2.47× performance per dollar improvement with our hardware. With architecture optimizations, FaaS.comm-opt with customized FPGA fabrics pushes the benefit to 7.78×, and FaaS.mem-opt with FPGA local DRAM and high-speed links to GPU further unleash the benefit to 12.58×.

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Section: Related Workmentioning

confidence: 99%

Hyperscale FPGA-as-a-service architecture for large-scale distributed graph neural network

Niu

Wang

et al. 2022

Proceedings of the 49th Annual International Symposium on Computer Architecture

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“…Other Related Hardware Accelerators: Many hardware accelerators [4,8,16,28,34,40,41,65] have also been designed for graph processing recently. Graphicionado [23] is the first ASICbased one and can reduce random memory accesses.…”

Section: Additional Related Workmentioning

confidence: 99%

TDGraph

Zhao

Yang

Liao

et al. 2022

Proceedings of the 49th Annual International Symposium on Computer Architecture

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Many solutions have been recently proposed to support the processing of streaming graphs. However, for the processing of each graph snapshot of a streaming graph, the new states of the vertices affected by the graph updates are propagated irregularly along the graph topology. Despite the years' research efforts, existing approaches still suffer from the serious problems of redundant computation overhead and irregular memory access, which severely underutilizes a many-core processor. To address these issues, this paper proposes a topology-driven programmable accelerator TDGraph, which is the first accelerator to augment the many-core processors to achieve high performance processing of streaming graphs. Specifically, we propose an efficient topology-driven incremental execution approach into the accelerator design for more regular state propagation and better data locality. TDGraph takes the vertices affected by graph updates as the roots to prefetch other vertices along the graph topology and synchronizes the incremental computations of them on the fly. In this way, most state propagations originated from multiple vertices affected by different graph updates can be conducted together along the graph topology, which help reduce the redundant computations and data access cost. Besides, through the efficient coalescing of the accesses to vertex states, TDGraph further improves the utilization of the cache and memory bandwidth. We have evaluated TDGraph on a simulated 64-core processor. The results show that, the state-of-the-art software system achieves the speedup of 7.1∼21.4 times after integrating with TDGraph, while incurring only 0.73% area cost. Compared with four cutting-edge accelerators, i.e., HATS, Minnow, PHI, and DepGraph, TDGraph gains the speedups of 4.6∼12.7, 3.2∼8.6, 3.8∼9.7, and 2.3∼6.1 times, respectively.

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“…As a result, the accelerators mainly focus on improving memory access efficiency, hiding communication latency, and/or reducing load imbalance. Recently, several domain-specific architectures are developed for graph computation, including Processing-In-Memory (PIM) based architectures [8], [46], [55], [57], accelerator for asynchronous [36], [51], [52] and iterative [38] graph processing.…”

Section: Introductionmentioning

confidence: 99%

IntersectX: An Efficient Accelerator for Graph Mining

Rao¹,

Chen²,

Yik³

et al. 2020

Preprint

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Graph mining applications try to find all embeddings that match specific patterns. Compared to the traditional graph computation, graph mining applications are computationintensive. The state-of-the-art method, pattern enumeration, specifically constructs the embeddings that satisfy the pattern, leading to significant speedups over the exhaustive check method. However, the key operation intersection poses challenges to conventional architectures and takes substantial execution time.In this paper, we propose IntersectX, a vertical approach to accelerate graph mining with stream instruction set extension and architectural supports based on conventional processor. The stream based ISA can considered as a natural extension to the traditional instructions for ordinary scalar values. We develop the IntersectX architecture composed of specialized mechanisms that efficiently implement the stream ISA extensions, including:(1) Stream Mapping Table (SMT) that records the mapping between stream ID and stream register; (2) the Stream Cache (S-Cache) that enables efficient stream data movements; (3) tracking the dependency between streams with a property of intersection; (4) Stream Value Processing Unit (SVPU) that implements sparse value computations; and (5) the nested intersection translator that generates micro-op sequences for implementing nested intersections. We implement IntersectX ISA and architecture on zsim [42]. We use 7 popular graph mining applications (triangle/three-chain/tailed-traingle counting, 3-motif mining, 4/5-clique counting, and FSM) on 10 real graphs. Our experiments show that IntersectX significantly outperforms our CPU baseline and GRAMER, a state-of-the-art graph mining accelerator. IntersectX's speedups over the CPU baseline and GRAMER [53] are on average 10.7×and 40.1×(up to 83.9×and 181.8×), respectively.

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GraphABCD: Scaling Out Graph Analytics with Asynchronous Block Coordinate Descent

Cited by 22 publications

References 47 publications

Hyperscale FPGA-as-a-service architecture for large-scale distributed graph neural network

Hyperscale FPGA-as-a-service architecture for large-scale distributed graph neural network

TDGraph

IntersectX: An Efficient Accelerator for Graph Mining

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