Graph colouring based multi pin net detailed routing for FPGA using SAT

Mukherjee, Shyamapada; Roy, Suchismita

doi:10.1109/iadcc.2013.6514241

Cited by 7 publications

(1 citation statement)

References 15 publications

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“…The historical congestion penalty h(n) is updated after every pathfinder routing iteration (5). The impact of h(n) on the total resource cost is controlled by the factor h f .…”

Section: Routing Schedulementioning

confidence: 99%

CRoute: A Fast High-Quality Timing-Driven Connection-Based FPGA Router

Vercruyce

Vansteenkiste

Stroobandt

2019

2019 IEEE 27th Annual International Symposium on Field-Programmable Custom Computing Machines (FCCM)

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FPGA routing is an important part of physical design as the programmable interconnection network requires the majority of the total silicon area and the connections largely contribute to delay and power. It should also occur with minimum runtime to enable efficient design exploration. In this work we elaborate on the concept of the connection-based routing principle. The algorithm is improved and a timing-driven version is introduced. The router, called CROUTE, is implemented in an easy to adapt FPGA CAD framework written in Java, which is publicly available on GitHub. Quality and runtime are compared to the state-of-the-art router in VPR 7.0.7. Benchmarking is done with the TITAN23 design suite, which consists of large heterogeneous designs targeted to a detailed representation of the Stratix IV FPGA. CROUTE gains in both the total wirelength and maximum clock frequency while reducing the routing runtime. The total wire-length reduces by 11% and the maximum clock frequency increases by 6%. These high-quality results are obtained in 3.4x less routing runtime.

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“…The historical congestion penalty h(n) is updated after every pathfinder routing iteration (5). The impact of h(n) on the total resource cost is controlled by the factor h f .…”

Section: Routing Schedulementioning

confidence: 99%