Solving constraints in FPGA detailed routing using SMT

Safar, Mona; Salem, Ashraf

doi:10.1109/icecs.2015.7440391

Search citation statements

Order By: Relevance

Paper Sections

Select...

Introduction1

Citation Types

Supporting

Mentioning

Contrasting

Year Published

2024

Publication Types

Select...

Article1

Relationship

Self Cite0

Independent1

Authors

Journals

Cited by 1 publication

(1 citation statement)

References 10 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…Modelling with SAT uses Boolean variables and Boolean algebra, and modelling with SMT requires non-Boolean variables. The formulas are submitted to solvers, who will attempt to generate assignments to the variables that satisfy the formulas [3,18]. Using SAT/SMT to model interconnects resources may simplify the TC generation [8], which is a promising feature.…”

Section: Introductionmentioning

confidence: 99%

Application dependent FPGA interconnect test method with small test configuration number using SMT net-grouping constraints

He,

Lai

2024

IEICE Electron. Express

View full text Add to dashboard Cite

An application dependent FPGA interconnect testing scheme is presented. The goal is to reduce the number of test configurations while keeping high fault coverage. Reduction is done by using SMT constraints that allow multiple nets as a group to use one input vector, so that the number of test configurations is reduced. Based on the complete fault model, a novel approach to generate SAT formulas, most notably dominant bridging faults, are explained to retain coverage. Experiments on FPGAs shown that this method yield on average 44% fewer configurations on circuits with 1000~100000 LUTs comparing with existing methods, with full fault coverage.

show abstract

Section: Introductionmentioning

confidence: 99%