Grain boundary assisted degradation and breakdown study in cerium oxide gate dielectric using scanning tunneling microscopy

Abstract

The presence of grain boundaries (GBs) in polycrystalline high-κ (HK) gate dielectric materials affects the electrical performance and reliability of advanced HK based metal-oxide-semiconductor devices. It is important to study the role of GB in stress-induced-leakage current (SILC) degradation and time-dependent dielectric breakdown of polycrystalline HK gate stacks. In this work, we present nanoscale localized electrical study and uniform stressing analysis comparing the electrical conduction properties at grain and GB locations for blanket cerium oxide (CeO2)-based HK thin films using scanning tunneling microscopy. The results clearly reveal higher SILC degradation rate at GB sites and their vulnerability to early percolation, supporting the phenomenon of GB-assisted HK gate dielectric degradation and breakdown.

Degradation of polycrystalline HfO2-based gate dielectrics under nanoscale electrical stress

“…By comparing the first measurements on the fresh locations (NC_IV1 and GB_IV1), it appears that the grains are less conductive than the GBs, in agreement with Ref. 15. Qualitatively different I-V dependencies measured on the GB and grain sites indicate that conduction through these structural features might be governed by different mechanisms.…”

“…On the contrary, when bias is applied to the grains (Fig. 3(a), NC_IV1-NC_IV4), the I-V curves progressively shift to lower voltages (stress-induced leakage current 15 ) and BD is not triggered until several I-V sweeps have been applied. However, when BD is reached, it seems stronger than on the GBs: NC_IV4 exhibits an ohmic characteristic indicating its metallic nature.…”

Characterization of defect evolution in ultrathin SiO2 layers under applied electrical stress

“…Defect evolution and degradation at the nanoscale level are however not well understood and are currently limited to theoretical studies. 17 Thus, the nanoscopic mechanisms and defect generation under electrical stress that lead to dielectric BD remain unclear. 17,18 Furthermore, it is debated in the literature whether SBD is a necessary precursor to induce HBD in an ultrathin dielectric layer.…”

“…17 Thus, the nanoscopic mechanisms and defect generation under electrical stress that lead to dielectric BD remain unclear. 17,18 Furthermore, it is debated in the literature whether SBD is a necessary precursor to induce HBD in an ultrathin dielectric layer. [19][20][21][22] To date, the dielectric breakdown behavior in MOSFET devices has been electrically characterized using bench-top technologies 9,16,[23][24][25] where local BD sites are further characterized post mortem using electron microscopy.…”

Heteroepitaxy of La2O3 and La2–xYxO3 on GaAs (111)A by Atomic Layer Deposition: Achieving Low Interface Trap Density

“…GaAs MOS devices with epitaxial dielectric layers should have a low interface trap density of states (D it ), since a perfect epitaxial interface is supposed to have no dangling bonds. Also, contrary to polycrystalline oxides, a perfect epitaxial oxide should contain no grain boundaries, 4 which preserves the desired features of the low leakage current and uniformity. However, growing epitaxial oxides on GaAs is rather challenging, since GaAs is neither chemically stable nor thermally stable: GaAs can be oxidized easily to form low quality surface oxides that compromise the interface quality; 5 and GaAs starts to lose As over 400 ˚C.…”