Graded SiGe-Channel Modulation-Doped p-Mosfets

Verdonckt-Vandebroek, S.; Crabbé, E.F.; Meyerson, B.S.; Harame, D.L.; Restle, P.J.; Stork, J.M.C.; Megdanis, A.C.; Stanis, C.; Bright, A. A.; Kroesen, G.M.W.; Warren, A.C.

doi:10.1109/vlsit.1991.706012

Cited by 21 publications

(9 citation statements)

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“…This means for circuit design that the best improvement in transistor characteristic can be reached in the gate voltage range near threshold. The maximum mobility values in our present transistors are lower than previously reported mobilities [4][5][6]. This is the result of the very high doping density at the surfaces.…”

Section: Mobilitycontrasting

confidence: 79%

“…The reason is impurity scattering due to high doping concentrations in the channel region, surface scattering at the SiOz interface and the presence of high electric fields in transistor operation. Using a GexSi~_x quantum well for the hole channel, mobility in the strained SiGe layer is higher due to the lower effective mass in the channel [1] and surface scattering is eliminated by the hole confinement in the buried SiGe channel [2][3][4][5][6].…”

Section: Introductionmentioning

confidence: 99%

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Characterization of SiGe quantum-well p-channel MOSFETs

Weidner

Hofmann

et al. 1995

J Mater Sci: Mater Electron

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Geo.~Si0.s Quantum Well p-MOSFETs with verythin gate oxides of 5 nm, 2.5 nm cap-layer and an optional Boron doped delta layer fabricated in a standard 0.6 gm CMOS process have been analysed by C-V and I-V measurements at different temperatures. The maximum low field hole mobility calculated from drain conductance was increased by 70% from 67 cm2/Vs for a reference Silicon epi transistor to 115 cm2/Vs at 300 K and by 100% from 110 cm2/Vs to 220 cm2/Vs at 98 K. These values were obtained at relatively high doping concentrations in the channel, the mobile channel charge was directly obtained from high and low frequency C-V curves. The influence of the net doping density in the channel region on the device characteristics is demonstrated. In the high electric field region the drain current in the saturation region was improved by 20% for the same threshold voltage.

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Section: Mobilitycontrasting

confidence: 79%

Section: Introductionmentioning

confidence: 99%

Characterization of SiGe quantum-well p-channel MOSFETs

Weidner

Hofmann

et al. 1995

J Mater Sci: Mater Electron

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“…However, the continuous scaling down of geometry requires the support of newer and more complex lithographic technology. Recently, high performance planar PMOSFET devices have been fabricated using compressively strained SiGe-on-Si exploiting higher in-plane hole mobility compared to bulk Si [3,4]. Some innovative device structures and processes have been proposed that achieve the high performance of these small geometry devices and yet can be made without requiring complicated fabrication techniques [1].…”

Section: Thtroductionmentioning

confidence: 99%

SiGe/Si vertical PMOSFET device design and fabrication

et al. 1997

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As channel lengths shrink continuously to smaller dimensions in order to improve performance and packing density, lithography, isolation, power supply and short channel effects have proved to be major limitations. Recently vertical MOSFETs (VMOS), also known as surround gate transistors, or 3-D side-wall transistors have been shown to overcome these process limitations. In this paper, we review the various VMOS technologies and applications and compare the performance of these devices to planar devices. We also present a novel deep submicron vertical SiGe/Si PMOSFET fabricated by Ge implantation. The Ge was implanted in the Si vertical channel to form a strained SiGe layer to increase drive current in P channel devices. PMOS drive current can be increased by about 100% compared to Si control devices. Thus, this technology offers CMOS circuit designers the flexibility to match PMOS and NMOS current drive capabilities, which was previously limited by the difference in electron and hole mobilities in Si. KEY WORDS Vertical MOSFET, SiGe/Si, Ge ion implantation SPIE Vol. 3212 • 0277-786X1971$1O.OO Downloaded From: http://proceedings.spiedigitallibrary.org/ on 06/20/2016 Terms of Use: http://spiedigitallibrary.org/ss/TermsOfUse.aspx

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“…Many groups have tried to use the surface-channel strained-Si MOSFET for both the nMOS and the pMOS devices, due to their high hole and electron mobilities. shows the buried-channel device with a modulation doping layer introduced to reduce impurity scattering in the channel [74]. The potential across the oxide can be written as…”

Section: Pmos Structuresmentioning

confidence: 99%

Nanoscale strained-Si/SiGe and double-gate MOSFET modeling

Chandrasekaran¹

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Seamless transition of devices across various topologies. 17 2.2 Piecewise (crosses) fc solutions, compared with iterative solution 23 (circle). 2.3 Piecewise (crosses) and unified regional (lines) $> solutions, compared 26 with iterative solution (circle). 2.4 Unified regional s solutions and the combined solutions sa 26 (accumulation/depletion) and t/> se ff(d\\ region) as well as its l st /2 n-order derivatives (inset). 2.5 The derivatives of Qb and its regional components with respective to 29 V g b and the inset shows smoothness of Cb g. 2.6 Unified regional bulk charge in accumulation (Qb.acc) and 31 depletion/inversion (Qb.ds) and the F^-dependent component (-C 0X Db"d). The inset shows tuning for charge neutrality at flat band. 2.7 Channel, drain, source capacitances from the derivatives of Q t , Qj, Q s 32 (inset), compared with Medici data (symbols). 3.1 The lattice structure of relaxed SiGe (top) and silicon (bottom). 35 3.2 Strained silicon on top of relaxed SiGe region. 36 3.3 Strain in silicon layer relieved due to misfit dislocations as it is grown 36 above the critical thickness. vii ATTENTION: The Singapore Copyright Act applies to the use of this document. Nanyang Technological University Library 3.4 (a) A six-fold degenerate silicon conduction-band minima (b) the two 37 dark ellipsoids are up in energy while the four white ellipsoids are down in energy, (c) The two perpendicular ellipsoids are down in energy while the four ellipsoids are up in energy. 3.5 Valence band under different strain condition. Strain is found to 38 remove the degeneracy between the LH band and the HH band. 3.6 Band offset between compressively strained Sio.7Geo.3 and silicon. 3.7 Band offset between tensile strained-Si and relaxed SiGe. 3.8 Calculated drift velocity at high electric field in strained and unstrained-Si. 3.9 Layer structures of strained-Si based nMOS devices 3.10 Layer structures of strained-Si based pMOS devices. 3.11 The maximum transconductance V, definition and I crit @ V t0 , used in the constant current definition. 3.12 Schematic of a surface channel strained-Si nMOSFET. 3.13 Schematic of a buried channels strained-Si nMOSFET. 3.14 Direct playback of the bulk charge model from bulk for x = 0.3, compared with Medici (circle), which shows the model missing the "plateau" and inaccuracy in the depletion region. 3.15 Hole concentrations (left axis) and surface potentials (right axis) at the 59 Si/Sic^ (solid) and Si/SiGe (dotted) interfaces extracted from the Medici device. Calculated VFBI and V FB 2 correspond directly to the viii ATTENTION: The Singapore Copyright Act applies to the use of this document. Nanyang Technological University Library numerically probed device parameters. 3.16 Band diagrams of the Medici device near the two calculated V FBI and 60 VFB2 gate-bias conditions, further supporting the definitions and physics built into the model (which physically relates to x, tsu and N Si parameters) 3.17 The two interpolation functions in relation to the two flat-band voltages 63 and AVj...

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Graded SiGe-Channel Modulation-Doped p-Mosfets

Cited by 21 publications

References 1 publication

Characterization of SiGe quantum-well p-channel MOSFETs

Characterization of SiGe quantum-well p-channel MOSFETs

SiGe/Si vertical PMOSFET device design and fabrication

Nanoscale strained-Si/SiGe and double-gate MOSFET modeling

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