GR-Noise Characterization of Ge pFinFETs With STI First and STI Last Processes

Abstract

This lettercharacterizes the generationrecombination noise of Ge pFinFETs, for three different integration schemes: shallow trench isolation (STI) first strained devices; STI last for relaxed and strained ones. It is shown that many Lorentzians exhibit a V GS -independent and thermally activated characteristic frequency. This points out that the responsible defects are located inside the fin and they are found for all studied process conditions. One type of defect with a time constant value of 10 ms at room temperature is process-independent. Regarding the defects, their activation energies and hole capture cross sections have been extracted for fin widths varying from planarlike devices to narrow ones. It is shown that the STI last strained and relaxed devices yield a surface trap density three orders of magnitude above the typical value obtained for a blanket wafer.

Split CV mobility at low temperature operation of Ge pFinFETs fabricated with STI first and last processes

“…The clear width dependence for the STI last sGe pFinFETs could be explained by several factors. It could point to the impact of the TDs on the hole mobility, which should increase with wider devices, resulting in a higher probability to contain a number of threading defects, which can act as scattering centers [32]. In addition, for narrower fins, the contribution of the (110) sidewalls to the transport over the top surface becomes more pronounced.…”

“…The STI last approach shows a rather weak variation of N INV as the temperature goes down to 77 K for both narrow and planar-like devices. On the other hand, the STI first approach shows a N INV variation even for wide devices and it significantly increases for narrow ones, meaning that the peak of the effective mobility shifts towards a lower inversion carrier density owing to the Coulomb scattering mechanism [32].…”

Low-Frequency Noise Assessment of Different Ge pFinFET STI Processes

“…On top of that, the humps presented in S ID indicate the presence of a GR-noise component, which gives insights where the traps are located: either into the gate dielectric or into the channel region [20]. The GR-noise has been reported in detail in [21] taking into consideration both studied STI processes. Apart from that, the plateau behavior in the f × S ID plots in Fig.…”

(Invited) Generation-Recombination Noise in Advanced CMOS Devices

“…P-channel FinFETs have also been evaluated, but they are fabricated in Ge channels, using different integration schemes, described in more detail elsewhere (12,13). The p-type Ge FinFETs have been fabricated on 300 mm Czochralski Si (100) wafers.…”

“…More recently, it has been applied to UTBOX SOI nMOSFETs (16), and SOI n- (7,17,18) and pFinFETs (19). Extension to the case of bulk FinFETs seems straightforward (13,20). In the case of a V GS -independent Lorentzian, one can determine the bulk trap parameters by measuring the corner frequency at constant current as a function of temperature.…”