Godson-T: An Efficient Many-Core Architecture for Parallel Program Executions

Abstract

Moore's law will grant computer architects ever more transistors for the foreseeable future, and the challenge is how to use them to deliver efficient performance and flexible programmability. We propose a many-core architecture, Godson-T, to attack this challenge. On the one hand, Godson-T features a region-based cache coherence protocol, asynchronous data transfer agents and hardware-supported synchronization mechanisms, to provide full potential for the high efficiency of the on-chip resource utilization. On the other hand, Godson-T features a highly efficient runtime system, a Pthreadslike programming model, and versatile parallel libraries, which make this many-core design flexibly programmable. This hardware/software cooperating design methodology bridges the high-end computing with mass programmers. Experimental evaluations are conducted on a cycle-accurate simulator of Godson-T. The results show that the proposed architecture has good scalability, fast synchronization, high computational efficiency, and flexible programmability.

New Methodologies for Parallel Architecture

“…64 homogeneous, in-order and dual-issue processing cores were integrated in Godson-T, a many-core processor [2] . Each processing core has a 16 KB 2-way set-associative private instruction cache and a 32 KB local memory.…”

Preliminary Investigation of Accelerating Molecular Dynamics Simulation on Godson-T Many-Core Processor

“…The 8-pipeline processing core supports 32-bit MIPS ISA (64-bit ISA will be supported in latter version) with synchronization instruction extensions. Key architectural features for achieving decent scalability and high performance include the following [4]:…”

GVE: Godson-T Verification Engine for many-core architecture rapid prototyping and debugging

“…Core: In-order and dual-issue processing cores, 16 Cores are interconnected by the 2-D mesh network, 1 Godson-T processor: A 64-Core many-core processor which is designed by our group. [1] 2 The 16-tile Godson-T tape-out project: The tape-out project of 16-core version of the Godson-T processor using SIMC 130nm library L2 Cache: 4 scattered L2 cache with lower bits interleave, GMIU: the Godson-T Mesh-network Interface Unit, GBIU: the Godson-T Bus Interface Unit, Sync: the synchronization manager,…”

“…[1] 2 The 16-tile Godson-T tape-out project: The tape-out project of 16-core version of the Godson-T processor using SIMC 130nm library L2 Cache: 4 scattered L2 cache with lower bits interleave, GMIU: the Godson-T Mesh-network Interface Unit, GBIU: the Godson-T Bus Interface Unit, Sync: the synchronization manager,…”