Glass panel processing for electrical and optical packaging

Schröder, Henning; Brusberg, Lars; Arndt-Staufenbiel, Norbert; Hofmann, J.; Marx, Sebastian

doi:10.1109/ectc.2011.5898578

Cited by 23 publications

(6 citation statements)

References 14 publications

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“…PCB embedded optical circuits can be implemented by a variety of alternative waveguide interconnect types including: 1) fibre-optic laminates [7], 2) planar polymer waveguides [8], [9] and 3) planar glass waveguides [10], whereby the choice of waveguide type is determined by its suitability to the link and the target application. For example, step-index multimode polymer waveguides would be unsuitable for longer high speed links, in which modal dispersion would limit performance and would also be unsuited to convey certain operational wavelengths (1310 nm or 1550 nm) over longer distances due to higher intrinsic absorbtion losses, though this can be mitigated by altering the polymer chemistry through perfluorination [11].…”

Section: Optical Waveguide Selectionmentioning

confidence: 99%

Embedded planar glass waveguide optical interconnect for data centre applications

Pitwon¹,

Schröder

Brusberg

et al. 2013

SPIE Proceedings

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Electro-optical printed circuit boards (EOCB) based on planar multimode polymer channels are limited by dispersion in the step-index waveguide structures and increased optical absorption at the longer telecom wavelengths [1]. We present a promising technology for large panel EOCB based on holohedrally integrated glass foils. The planar multimode glass waveguides patterned into these glass foils have a graded-index structure, thereby giving rise to a larger bandwidthlength product compared to their polymer waveguide counterparts and lower absorbtion at the longer telecom wavelengths. This will allow glass waveguide based EOCBs to support the future bandwidth requirements inherent to large scale data centre and high performance computer subsystems while not incurring the same dispersion driven penalties on interconnect length or loss dependence on wavelength. To this end glass foil structuring technologies have been developed that are compatible with industrial PCB manufa cturing processes. Established processes as well as new approaches were analysed for their eligibility and have been applied to the EOCB process. In addition a connector system has been designed, which would allow optical pluggability to glass waveguide EOCBs

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Section: Optical Waveguide Selectionmentioning

confidence: 99%

Embedded planar glass waveguide optical interconnect for data centre applications

Pitwon¹,

Schröder

Brusberg

et al. 2013

SPIE Proceedings

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“…The Chemical-Mechanical Planarization (CMP) process is used to remove the copper overburden. The major steps for the TSV process are summarized as following [5][6][7][8][9][10][11][12][13][14][15][16][17][18][19][20][21][22][23]:…”

Section: Large Size Silicon Interposermentioning

confidence: 99%

Addressing bandwidth challenges in next generation high performance network systems with 3D IC integration

Xue

et al. 2012

2012 IEEE 62nd Electronic Components and Technology Conference

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The bandwidth for high performance networking switches and routers increases two to ten times in every new generation. This in turn drives the bandwidth requirements for the Application Specific Integrated Circuits (ASICs) and their external memory devices designed for the high performance network systems. 3D IC integration with its low power, high density and high bandwidth advantages is proposed to address the bandwidth challenges between the ASIC and its external memory. This paper presents a novel 3D IC architecture that includes a silicon interposer with Through-Silicon-Vias (TSV) and interconnect wiring layers on both sides of the silicon interposer. An ASIC chip measured at 22 mm x 18 mm x 0.4 mm is attached on top of the silicon interposer while two smaller memory chips with a size of 10 mm x 10 mm x 0.4 mm are attached to the bottom of the silicon interposer with micro-bump interconnections. A unique, double-sided Chip to Chip (C2C) joining process is developed to enable the ASIC and memory integration in true 3D System-in-Package (SiP) format. This 3D IC architecture will help to overcome the size limitation of the current silicon interposers due to the reticle size used in the lithographic wafer processing.The 3D IC stack is assembled on an organic package substrate with conventional solder bumps. Communications between the top ASIC die and the bottom memory dice are made through the TSVs and the wiring layers of the silicon interposer. Thermal and thermo-mechanical analysis of the 3D IC stack are used to evaluate the package thermal performance and for optimizing material selection and package reliability. Both the modeling and experimental characterization results are used to gain insights into the 3D IC technology for addressing the ASIC and memory bandwidth challenges and to develop the best practice for ASIC and memory integration for next generation high performance network systems.

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“…In addition to the silicon interposer packaging technology, alternative glass carrier technologies have been investigated by several authors, e.g., in [2]- [3]. Silicon interposer's multi-level wiring enables a tight integration of an optical module's VCSELs, PDs, and ICs.…”

Section: Introductionmentioning

confidence: 99%

High-speed signaling performance of multilevel wiring on glass substrates for 2.5-D integrated circuit and optoelectronic integration

Rimolo-Donadío

Budd

et al. 2013

2013 IEEE 63rd Electronic Components and Technology Conference

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This paper reports on the evaluation of high-speed signaling performance of multilevel metallic interconnects on glass substrates. The wafer fabrication, transfer process, and passive electrical characterization of interconnects are addressed. Measurement results demonstrate less than 5 dB/cm insertion loss below 20 GHz. Moreover, 2-level wiring on glass with inter-level vias is utilized to implement 3.6-mm long transmission lines that connect high-speed transceivers and optoelectronic devices in a VCSEL-based optoelectronic fiber link. The relative performances of diverse configurations with and without wiring on glass are compared. Error-free link operation at a bit-error-rate (BER) of 10 -12 is demonstrated up to 30 Gb/s with ~3 dB sensitivity penalty for the link with glass carrier transmission lines.

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Glass panel processing for electrical and optical packaging

Cited by 23 publications

References 14 publications

Embedded planar glass waveguide optical interconnect for data centre applications

Embedded planar glass waveguide optical interconnect for data centre applications

Addressing bandwidth challenges in next generation high performance network systems with 3D IC integration

High-speed signaling performance of multilevel wiring on glass substrates for 2.5-D integrated circuit and optoelectronic integration

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