Gigabit transmitter array modules on silicon waferboard

Armiento, Craig; Negri, A.; Tabasky, M.; Boudreau, R.; Rothman, M.; Fitzgerald, T. W.; Haugsjaa, Paul O.

doi:10.1109/33.206933

Cited by 53 publications

(8 citation statements)

References 7 publications

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“…This analysis was loosely based on an optical transceiver introduced by GTE laboratories. 3 One would expect an architecture to be favorably comparable to the electrical alternative for interconnection levels of chip to chip and above, and for lengths over 1.5 cm, where signal regeneration is required in electrical interconnects. For the particular transceiver, the transmitter consists of four channels driven by a six-element laser diode array, coupled to single-mode optical fibers passively aligned by the use of V-grooves for the fibers and the use of reactiveion-etching-defined pedestals and stops for placement of the components on a silicon waferboard; the receiver portion consists of metal-semiconductor-metal ͑MSM͒ photodetectors also passively aligned over an etched metallized silicon mirror that receives the signal from the fibers inside the V-grooves.…”

Section: Discussionmentioning

confidence: 99%

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Parameter extraction for a figure-of-merit approach for the comparison of optical interconnects

et al. 1998

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A methodology is described for parameter extraction from modeling for the determination of the appropriate figures of merit (FOMs) to be used for comparisons between different architectures of optical interconnects and their electrical counterparts. The key FOM selected for performance is that of data throughput, defined as the product of bitrate and interconnect length. Parameter extraction proceeds through modeling of a prototype optical transceiver introduced by GTE laboratories. Optical power budget modeling is performed as it applies to a simple basic optical interconnect, which can then be extended to the modeling of arrays, by incorporating channel crosstalk limitations. Through this modeling, the specific limitations to the data throughput are explored and several trade-offs such as those between gain and speed, power and delay-times, and power and bit error rate (BER) are quantified. © 1998 Society of Photo-Optical Instrumentation Engineers. [S0091-3286(98)

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Section: Discussionmentioning

confidence: 99%

“…However, due to its own parasitics, the photodetector exhibits a minimum in its response time and integrates the signal. Therefore, the bottleneck is set by the power budget analysis in conjunction with the dissipated power/heating considerations and bit rates up to 1 Gb/s, as reported by Armiento et al 3 can indeed be predicted by the model.…”

Section: ͑5͒mentioning

confidence: 91%

Parameter extraction for a figure-of-merit approach for the comparison of optical interconnects

et al. 1998

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“…The module employed two custom fabricated chips, a ridge waveguide laser array and an integrated laser driver array circuit [2]. Passive alignment of the lasers to the fibers was accomplished through the use of physical alignment structures that were precision etched into the surface of the silicon waferboard and the laser array chip.…”

Section: A Fabrication Of the Array Transmitter Modulementioning

confidence: 99%

Silicon waferboard-based single-mode optical fiber interconnects

Haugsjaa¹,

Duchene²,

Mehr³

et al. 1996

IEEE Trans. Comp., Packag., Manufact. Technol. B

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In an extension of previous work, hybrid integration utilizing silicon waferboard plafforms has been shown to be useful in building complete single-mode, optical fiber interconnect links. The fabrication and testing of high-performance optical interconnect array transmitter modules and receiver modules is described in this paper. The silicon waferboards include alignment features for passively aligning laser arrays and turning mirrors for backside illumination of metal-semiconductor-metal (MSM) detectors. Transmission rates of 1.4 Gb/s per fiber over single-mode optical fiber have been demonstrated. The fourchannel link developed in this work was tested over a distance of 1 km and exhibited a link margin of greater than 11 dB. The bit error ratio was less than and the crosstalk for adjacent channel traffic was about -20 dB at 1 GHz. This effort has confirmed the feasibility of employing silicon waferboard passive optical alignment techniques to potentially lower the cost of high speed optical interconnects.Index Terms-Optical interconnects, passive aliment, metalsemiconductor-metal detectors, laser array, silicon waferboard, optoelectronic arrays

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“…More and more optoelectronic assemblies are being soldered and the processes have been reviewed by Basavanhally [1], and Tan and Lee [2]. These processes can be broken into the following four categories: (1) solder the assembly with no precision self-alignment [3,4], (2) solder and allow self-alignment with no mechanical stops [3][4][5][6][7][8][9][10], (3) solder and allow self-alignment with one mechanical stop [11][12][13], and (4) solder and allow self-alignment with two mechanical stops [14]. Self-aligning soldering technology is widely used for optoelectronic packaging because of its low cost.…”

Section: Introductionmentioning

confidence: 99%

Gas flow effects on precision solder self-alignment

Gershovich²,

Lee³

1997

IEEE Trans. Comp., Packag., Manufact. Technol. C

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Self-aligning soldering technology is being developed for low cost, passive, precision optical alignments. To avoid contamination problems, the solder reflow process must use reacting or inert gas instead of chemical flux materials. Since the accuracy of these optical alignments should reach the range of a few micrometers (µm), the gas flow may affect the aligning process. Therefore, the effects of the gas flow on the self-aligning process must be understood. The experiments described show that gas flow effects do exist. The top plate, 8.4 mm × 8.4 mm, can be moved by the gas flow by as much as 4.5 µm and 7.8 µm at gas flow rates of 2.5 L/min and 5.0 L/min, respectively. The numerical analysis in this study models the gas flow effects for a wide range of chip sizes, solder geometry, and gas flow direction. In the numerical analysis, fluid computation and solder force calculation are conducted to study the gas flow effects on chip displacement that is the distance away from the well aligned position along the gas flow direction. The results show that the gas flow effects are related to many factors including chip size, gas flow rate, solder height, and flow direction. For a one-dimensional laser array, these effects are negligible because the chip size is very small. However, for a chip larger than 5 mm × 5 mm, the effects should be controlled for micron-level precision alignment.

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Gigabit transmitter array modules on silicon waferboard

Cited by 53 publications

References 7 publications

Parameter extraction for a figure-of-merit approach for the comparison of optical interconnects

Parameter extraction for a figure-of-merit approach for the comparison of optical interconnects

Silicon waferboard-based single-mode optical fiber interconnects

Gas flow effects on precision solder self-alignment

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