Geometry dependent tunnel FET performance - dilemma of electrostatics vs. quantum confinement

Si/Ge hetero-structure nanotube tunnel field effect transistor

“…20,21 In the case of the NT, we have used average circumference (p  (CG dia þ NT w )), where CG dia and NT w are the nanotube core-gate diameter and thickness, respectively. This leads to a fair comparison since as we scale down the inner core gate diameter, CG dia , to zero, the normalization length becomes (p  NT w ), which is essentially the circumference of a NW with a diameter equal to the NT thickness, d NW ¼ NT w. This is also consistent with previous reports in the literature, where SG, DG, and GAA architectures are compared at a body thickness, measured normal to the gate oxide, equal to the diameter of the NW, d NW , to study the effect of device geometry on the BTBT rates and scanning tunneling length, k. 5 The non-normalized drain current of the NT TFET, 6.1 lA is 18 times than that of the NW TFET, 0.34 lA, while the normalized drain current of the NT TFET, 18 lA/lm is 1.6 than that of the normalized NW-TFET drain current, 11 lA/lm. The SS values for both devices are shown in Fig.…”

“…5 Hence, the BTB generation rate peaks within the Ge gate-to-source overlap region for the NW TFET. As for the NT TFET, although vertical tunneling is still noticed within the overlap region, BTB generation rate peaks on the Si side of the Si/Ge interface due to lateral tunneling.…”

“…3 The GAA NW TFET architecture, however, is able to provide lower point SS values as noted above which is due to the tighter electrostatic control and lower scaling tunneling length, k, as expected from the WKB approximation when compared to the DG and SG architectures. 5 This should potentially lead to higher normalized drain current for the GAA NW TFET; however, in reality, this was not the case. Therefore, we investigated the electron band-to-band generation profile for both the NT and NW TFETs in Fig.…”

“…It has been shown that the highest tunneling rate and hence the lowest k values were found for the gate-all-around (GAA) architecture, while ultra-thin body (UTB) double gate (DG) and single gate planar (SG) UTBs have shown higher k values. 5 However, the theoretical study has also shown that when the transistor channel thickness is scaled down to less than or equal to 10 nm, the k value of the DG architecture approaches that of the GAA around architecture, 3.8 nm vs. 2.4 nm for 10 nm body thickness. The k values are even equal at body thickness of 2.5 nm.…”

“…The k values are even equal at body thickness of 2.5 nm. 5 From device architecture perspective, we have recently shown the unique advantages of conventional channel material silicon (Si) based core/shell gated nanotube (NT) architecture for controlling the device channel over the GAA nanowire (NW) architecture. The nanotube architecture mimics the GAA NW devices by having an outer (shell) gate, as well as, an inner (core) gate inside the nanowire making it a hollow cylindrical structure.…”