Generating Core in Rough Set Theory: Design and Implementation on FPGA

Kopczynski, Maciej; Grzes, Tomasz; Stepaniuk, Jarosław

doi:10.1007/978-3-319-08729-0_20

Cited by 13 publications

(4 citation statements)

References 8 publications

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“…Core calculation unit is responsible for hardware support related to calculating subcores for given parts of decision table. Authors have used modified version of sequential core hardware calculation unit described in paper [4]. This unit has been extended in order to allow processing large datasets.…”

Section: Hardware Implementationmentioning

confidence: 99%

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Core for Large Datasets: Rough Sets on FPGA

Kopczynski

Grzes

Stepaniuk

2016

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In this paper we propose the FPGA and softcore CPU based device for large datasets core calculation using rough set methods. Presented architecture has been tested on two real datasets by downloading and running presented solution inside FPGA. Tested datasets had 1 000 to 10 000 000 objects. The same operations were performed in software implementation. Obtained results show the big acceleration in computation time using hardware supporting core generation in comparison to pure software implementation.

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Section: Hardware Implementationmentioning

confidence: 99%

“…More detailed summary of the existing ideas and hardware implementations of rough set methods can be found in [2] and in [13]. Previous authors' research results focused on this subject can be found in [3,4,12].…”

Section: Introductionmentioning

confidence: 99%

Core for Large Datasets: Rough Sets on FPGA

Kopczynski

Grzes

Stepaniuk

2016

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“…Authors are working on fully operational System-on-Chip (SoC) including central processing unit based on Altera NIOS II core implemented in Stratix III FPGA and co-processor for rough sets calculations. More details on previous authors' work can be found in [1,[5][6][7]14].…”

Section: Introductionmentioning

confidence: 99%

Hardware Supported Rough Sets Based Rules Generation for Big Datasets

Kopczynski

Grzes

Stepaniuk

2016

Computer Information Systems and Industrial Management

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In this paper we propose a combination of capabilities of the Field Programmable Gate Arrays based device and PC computer for rough sets based data processing resulting in generation of decision rules. Solution is focused on big datasets. Presented architecture has been tested in programmable unit on real datasets. Obtained results confirm the significant acceleration of the computation time using hardware supporting rough set operations in comparison to software implementation.

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“…Their results show a significant increase in the speed of data processing. In [26], they have shown three variants of discernibility matrix implementation. Authors have shown time required for computing reducts and cores for all three methods.…”

Section: F Maciej Kopczynski ´S Et Al Computation Of Reduct Andmentioning

confidence: 99%

Design and Implementation of Rough Set Algorithms on FPGA: A Survey

Tiwari¹,

Kothari²

2014

ijarai

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Abstract-Rough set theory, developed by Z. Pawlak, is a powerful soft computing tool for extracting meaningful patterns from vague, imprecise, inconsistent and large chunk of data. It classifies the given knowledge base approximately into suitable decision classes by removing irrelevant and redundant data using attribute reduction algorithm.Conventional Rough set information processing like discovering data dependencies, data reduction, and approximate set classification involves the use of software running on general purpose processor. Since last decade, researchers have started exploring the feasibility of these algorithms on FPGA. The algorithms implemented on a conventional processor using any standard software routine offers high flexibility but the performance deteriorates while handling larger real time databases. With the tremendous growth in FPGA, a new area of research has boomed up. FPGA offers a promising solution in terms of speed, power and cost and researchers have proved the benefits of mapping rough set algorithms on FGPA. In this paper, a survey on hardware implementation of rough set algorithms by various researchers is elaborated.

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Generating Core in Rough Set Theory: Design and Implementation on FPGA

Cited by 13 publications

References 8 publications

Core for Large Datasets: Rough Sets on FPGA

Core for Large Datasets: Rough Sets on FPGA

Hardware Supported Rough Sets Based Rules Generation for Big Datasets

Design and Implementation of Rough Set Algorithms on FPGA: A Survey

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