Generalized Relationship Between Frequency Response and Settling Time of CMOS OTAs: Toward Many-Stage Design

Mohammed, Mahmood; Roberts, G.W.

doi:10.1109/tcsi.2021.3110106

Cited by 5 publications

(9 citation statements)

References 20 publications

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“…Therefore, such P-Z pairs' arrangement has not been introduced in the literature before. However, a fundamental theory has been introduced in [12] revealing that the impact of the P-Z doublets on the settling time of CMOS OTAs can be minimized by positioning the open-loop zeros (i.e., ω Zi ) at low frequencies provided there is sufficient DC gain. Consequently, this theory revealed untapped opportunities to cascade many gain stages, which will be exploited in this work.…”

Section: Maximizementioning

confidence: 99%

“…However, the limitation of the upper value of ω t is ω Ppar , seen in Eqn. (12) and Fig. 6(a); as there is no full-design control over this parasitic pole.…”

Section: (A)mentioning

confidence: 99%

“…Instead of deriving new equations for the poles and zeros for each stage separately, and by knowing that the P-Z pairs have an inverse relationship with R C and C C , the values for C C which was found for the 2-stage OTA can be adjusted according to the constraint equations listed below [12]:…”

Section: B Scaling the Two-stage R-c Compensation Circuit For N ≥ 3 U...mentioning

confidence: 99%

“…Consequently, many CMOS OTA architectures have been proposed in the literature to meet the various design requirements to drive a wide range of C L while achieving adequate DC gain. Despite having stability challenges once configured in closed loop, cascading gain stages is believed by the authors to be the preferred method to achieve sufficient DC gain in modern CMOS technology processes operating with low voltage supply levels [12], [13]. Fig.…”

Section: Introductionmentioning

confidence: 99%

See 3 more Smart Citations

Scalable Multi-Stage CMOS OTAs With a Wide C_L-Drivability Range Using Low-Frequency Zeros

Mohammed

Roberts

2023

IEEE Trans. Circuits Syst. I

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This work introduces a multi-stage CMOS OTA design technique that allows cascading identical gain stages (for arbitrarily scalable high DC gain) while driving an ultra-wide range of capacitive loads (C L s). At the heart of the proposed design is a new frequency compensation technique (FCT) that relies on low-frequency left-half-plane zeros to allow the proposed OTA to operate for a desired closed-loop behavior. In this work, classical gain-stages (i.e., differential pair and common source transistors) are used to design fully-differential 2-, 3-, 4-and 5-stage CMOS OTAs. The proposed 2-to-4-stage designs have been fabricated in TSMC 65 nm CMOS process and the measurement results show that the 2-stage OTA is achieving a DC gain of 50 dB with a C L -drivability ratio (i.e., C L,max /C L,min ) of 10,000×, the 3-stage OTA is achieving a DC gain of 70 dB with a C L -drivability of 1,000,000×, and the 4-stage OTA is achieving a DC gain of 90 dB with a C L -drivability of 1,000,000×. This is a 10-to-1000-time improvement in the state-of-the-art, as the highest C L -drivability reported to date is 1000×. Accordingly, the proposed OTAs can cover a wider range of applications than any other reported works.

show abstract

Section: Maximizementioning

confidence: 99%

“…However, the limitation of the upper value of ω t is ω Ppar , seen in Eqn. (12) and Fig. 6(a); as there is no full-design control over this parasitic pole.…”

Section: (A)mentioning

confidence: 99%

Section: B Scaling the Two-stage R-c Compensation Circuit For N ≥ 3 U...mentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

See 2 more Smart Citations

Scalable Multi-Stage CMOS OTAs With a Wide C_L-Drivability Range Using Low-Frequency Zeros

Mohammed

Roberts

2023

IEEE Trans. Circuits Syst. I

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“…The resistor R C is finally sized such that the first zero is positioned at the desired α×GBW location higher or lower than the GBW frequency [7], thus from ( 8) and ( 26) we get…”

Section: Design Guidelinesmentioning

confidence: 99%

Frequency Compensation of Three-Stage OTAs to Achieve Very Wide Capacitive Load Range

2022

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This paper proposes an optimal design approach for three-stage amplifiers driving an ultra-wide range of load capacitor. To this end, efficient state-of-the-art solutions have been combined to develop a power-efficient frequency compensation solution. High-speed feedback pathways relying on Miller capacitors and current buffers are implemented within the amplifier scheme to push the non-dominant poles to high frequencies for small to medium load capacitors. A small resistor is also shared between the two pathways to improve the stability regardless of the load capacitor. A serial R-C branch is then added to extend the lower limit of load drive capability to small load capacitors. Gain margin is, for the first time in literature, analytically evaluated and included in the design phase. A prototype of the proposed amplifier is fabricated in 65-nm CMOS process with active area of 0.0017 mm 2 and 1.15 pF total compensation capacitance. It can drive the load capacitor range from 200 pF to 100 nF, while drawing a quiescent current of 7.4 µA from a 1.2-V input voltage supply. A unity-gain frequency of 1.67 MHz was measured with an average slew-rate of 1.31 V/µs, when the proposed amplifier is wired in unity-gain configuration to drive a 500-pF load capacitor.

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An NMOS LDO With TM-MOS and Dynamic Clamp Technique Handling Up To Sub-10-μs Short-Period Load Transient

Ming,

Kuang,

Gong

et al. 2024

IEEE J. Solid-State Circuits

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Generalized Relationship Between Frequency Response and Settling Time of CMOS OTAs: Toward Many-Stage Design

Cited by 5 publications

References 20 publications

Scalable Multi-Stage CMOS OTAs With a Wide C_L-Drivability Range Using Low-Frequency Zeros

Scalable Multi-Stage CMOS OTAs With a Wide C_L-Drivability Range Using Low-Frequency Zeros

Frequency Compensation of Three-Stage OTAs to Achieve Very Wide Capacitive Load Range

An NMOS LDO With TM-MOS and Dynamic Clamp Technique Handling Up To Sub-10-μs Short-Period Load Transient

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Generalized Relationship Between Frequency Response and Settling Time of CMOS OTAs: Toward Many-Stage Design

Cited by 5 publications

References 20 publications

Scalable Multi-Stage CMOS OTAs With a Wide CL-Drivability Range Using Low-Frequency Zeros

Scalable Multi-Stage CMOS OTAs With a Wide CL-Drivability Range Using Low-Frequency Zeros

Frequency Compensation of Three-Stage OTAs to Achieve Very Wide Capacitive Load Range

An NMOS LDO With TM-MOS and Dynamic Clamp Technique Handling Up To Sub-10-μs Short-Period Load Transient

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Product

Resources

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Scalable Multi-Stage CMOS OTAs With a Wide C_L-Drivability Range Using Low-Frequency Zeros

Scalable Multi-Stage CMOS OTAs With a Wide C_L-Drivability Range Using Low-Frequency Zeros