GCM implementations of Camellia-128 and SMS4 by optimizing the polynomial multiplier

Martínez-Herrera, Alberto F.; Mancillas-López, Cuauhtémoc; Mex-Perera, Carlos

doi:10.1016/j.micpro.2016.04.006

Cited by 9 publications

(11 citation statements)

References 7 publications

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“…In the field of communications, with the improvement of bandwidth and performance requirements, traditional buses have been gradually phased out. At this time, the PCIe bus as a third-generation interconnect bus successfully solved the bottleneck problem during high-speed data transmission and obtained good applications [ 5 , 6 ], which also means that the era when the traditional parallel bus started to develop towards the high-speed serial bus has arrived. The performance of the PCIe bus is excellent.…”

Section: Introductionmentioning

confidence: 99%

Decision Tree-Based Sensitive Information Identification and Encrypted Transmission System

Liu

Yang

et al. 2020

Entropy

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With the advent of the information age, the effective identification of sensitive information and the leakage of sensitive information during the transmission process are becoming increasingly serious issues. We designed a sensitive information recognition and encryption transmission system based on a decision tree. By training sensitive data to build a decision tree, unknown data can be classified and identified. The identified sensitive information can be marked and encrypted to achieve intelligent recognition and protection of sensitive information. This lays the foundation for the development of an information recognition and encryption transmission system.

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Section: Introductionmentioning

confidence: 99%

Decision Tree-Based Sensitive Information Identification and Encrypted Transmission System

Liu

Yang

et al. 2020

Entropy

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“…A detailed study has been carried out on the existing hardware designs of MISTY1, KASUMI, AES, SHA-1, CAMELLIA and SAFER [5][6][7][8][9][10][11][12][13][14][15][16][17][18][19][20][21][22]. The review covered the comparison of performance parameters i.e.…”

Section: Introductionmentioning

confidence: 99%

“…area, speed and frequency. For high speed architectures, the commonly employed schemes include Look-Up Tables (LUTs) or Block RAMs (BRAMs) implementation for s-boxes [10], [11], [19], [20]. In addition, optimizations are made for path delay reduction by effective pipe-lines implementation [11], [19].…”

Section: Introductionmentioning

confidence: 99%

Area-Efficient Hardware Architectures of MISTY1 Block Cipher

Yasir¹,

Wu²,

Chen³

et al. 2018

RADIOENGINEERING

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In this paper, state-of-the-art hardware implementations of MISTY1 block cipher are presented for areaconstrained wireless applications. The proposed MISTY1 architectures are characterized of highly optimized transformation functions i.e. FL and {FO-XOR-EKG}. The FL function re-utilizes logic AND-OR-XOR combinations whereas {FO-XOR-EKG} function explores 2 × compact design schemes for s-boxes implementation. A Combined Substitution Unit (CSU) and threshold area implementation are proposed for s-boxes based on Boolean reductions and Common Sub-expression Eliminations (CSEs). Besides, {FO-XOR-EKG} function is designed for manifold operations of FO / FI functions, 32-bit XOR operation and extended key generation thereby reducing the area. Hardware implementations on ASIC 180nm, 1.8V standard library cell realized compact and threshold MISTY1 designs constituting 1853 and 1546 NAND gates with throughput values of 41.6 Mbps and 4.72 Mbps respectively. A comprehensive comparison with existing cryptographic hardware designs establishes that the proposed MISTY1 architectures are the most area-efficient implementations till date.

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“…The design and optimization of cryptographic algorithms have been studied in detail keeping in view the application requirements for low area, high speed or achieving a trade-off between area and speed [2,3,4,5,6,7,8,9,10,11]. For low area design, the commonly adopted methods include re-utilization of logic blocks and s-boxes optimization [2,3,4,5,6,7].…”

Section: Introductionmentioning

confidence: 99%

“…The compact MISTY1, however are highly unsuitable for high speed applications having low throughput values. Contrary to area-efficient design schemes, encryption algorithms including AES, KASUMI, CAMELLIA and MISTY1 employ RAMs/LUTs/combinational logic to substitute s-boxes using pipe-lined architecture for high speed implementations [7,8,9,10,11]. It is found that the non-optimized high-speed architectures implementing straight-forward pipelines require large area thus reducing the efficiency [7,11].…”

Section: Introductionmentioning

confidence: 99%

FPGA based highly efficient MISTY1 architecture

Yasir

Chen

et al. 2017

IEICE Electron. Express

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This letter proposes highly efficient MISTY1 8-rounds pipelined architecture for wireless networks. A novel methodology is adopted for implementation of MISTY1 substitution functions by optimizing S9 and S7 LUTs (Look-Up Tables) to minimize the silicon area. Besides, a key module FI function is compliant to double edge-trigger the optimized S9 LUTs. This leads to substantial reduction in the pipeline requirements for the proposed hardware architecture. For path delay reduction, logic modifications are made in FI and FO functions realizing efficient and high-speed MISTY1 implementation. FPGA implementation on Xilinx FPGA, Virtex 7 xc7vx690t yielded a throughput value of 16.3 Gbps covering area of 1265 CLB slices.

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GCM implementations of Camellia-128 and SMS4 by optimizing the polynomial multiplier

Cited by 9 publications

References 7 publications

Decision Tree-Based Sensitive Information Identification and Encrypted Transmission System

Decision Tree-Based Sensitive Information Identification and Encrypted Transmission System

Area-Efficient Hardware Architectures of MISTY1 Block Cipher

FPGA based highly efficient MISTY1 architecture

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