GAUT: An architectural synthesis tool for dedicated signal processors

Martin, Éric; Sentieys, Olivier; Dubois, Hèléne; Philippe, Jean-Luc

doi:10.1109/eurdac.1993.410610

Cited by 58 publications

(29 citation statements)

References 6 publications

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“…In order to address the productivity issue, much research has focused on high-level synthesis (HLS) tools [22], [2], [9], [1], [7], which input the system description in higher level language, such as C programming language (C). Unfortunately, so far none of these tools come close to the speedups obtained by manual design.…”

Section: Introductionmentioning

confidence: 99%

Automatic Generation of FPGA-Specific Pipelined Accelerators

Alias

Pasca

Plesco

2011

Lecture Notes in Computer Science

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Abstract-Recent increase in the complexity of the circuits has brought high-level synthesis tools as a must in the digital circuit design. However, these tools come with several limitations, and one of them is the efficient use of pipelined arithmetic operators. This paper explains how to generate efficient hardware with pipelined operators for regular codes with perfect loop nests. The part to be mapped to the operator is identified, then the program is scheduled so that each operator result is available exactly at the time it is needed by the operator, keeping the operator busy and avoiding the use of a temporary buffer. Finally, we show how to generate the VHDL code for the control unit and how to link it with specialized pipelined floating-point operators generated using open-source FloPoCo tool. The method has been implemented in the Bee research compiler and experimental results on DSP kernels show promising results with a minimum of 94% efficient utilization of the pipelined operators for a complex kernel.

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Section: Introductionmentioning

confidence: 99%

Automatic Generation of FPGA-Specific Pipelined Accelerators

Alias

Pasca

Plesco

2011

Lecture Notes in Computer Science

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“…This is achieved because EDFG allows for data and conditional semantics to be handled in the same way, and thus the exploitation of potential design parallelism can be maximized. The processed graph is then given to the GAUT HLS tool [22] to perform operator selection and allocation, scheduling and binding. This methodology is rather more suitable for dataflow dominated systems such as video streaming and linear DSP algorithms.…”

Section: Related Workmentioning

confidence: 99%

Seamless Signal Processing Block Implementation Using the Cubed-C Design Environment

Dossis¹

2017

IRATJ

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Design environments and automated CAD systems are proliferated nowadays with various preferences and restrictions in their work environments. One serious problem of automated high-level synthesis tools is their inability of at least difficulty to use for low, bit level functions such as signal processing blocks. Here the Cubed-C environment is used for the rapid implementation of a number of low level functions and blocks such as UARTs without difficulty. Cubed-C is a full-strength high-level synthesis CAD system; nevertheless, its structure and properties make it particularly suitable for this type of fine-grained applications. The experiments in this paper prove that the Cubed-C synthesis tools are particularly suitable for both complex and for low, bit level signal coding functions.

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“…Synthesis from C to hardware has been a topic of intensive research with developments such as the Spark framework [30], GAUT tool of LABSTICC [31], and Catapult C from Mentor Graphics [32]. However, C program is designed to execute sequentially, and it still remains a difficult problem to generate efficient HDL codes from C, especially for DSP applications.…”

Section: Dataflow Modeling and High-level Synthesismentioning

confidence: 99%

Pipeline synthesis and optimization of FPGA-based video processing applications with CAL

Rahman

Prihozhy

Mattavelli

2011

J Image Video Proc.

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This article describes a pipeline synthesis and optimization technique that increases data throughput of FPGAbased system using minimum pipeline resources. The technique is applied on CAL dataflow language, and designed based on relations, matrices, and graphs. First, the initial as-soon-as-possible (ASAP) and as-late-aspossible (ALAP) schedules, and the corresponding mobility of operators are generated. From this, operator coloring technique is used on conflict and nonconflict directed graphs using recursive functions and explicit stack mechanisms. For each feasible number of pipeline stages, a pipeline schedule with minimum total register width is taken as an optimal coloring, which is then automatically transformed to a description in CAL. The generated pipelined CAL descriptions are finally synthesized to hardware description languages for FPGA implementation. Experimental results of three video processing applications demonstrate up to 3.9× higher throughput for pipelined compared to non-pipelined implementations, and average total pipeline register width reduction of up to 39.6 and 49.9% between the optimal, and ASAP and ALAP pipeline schedules, respectively.

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GAUT: An architectural synthesis tool for dedicated signal processors

Cited by 58 publications

References 6 publications

Automatic Generation of FPGA-Specific Pipelined Accelerators

Automatic Generation of FPGA-Specific Pipelined Accelerators

Seamless Signal Processing Block Implementation Using the Cubed-C Design Environment

Pipeline synthesis and optimization of FPGA-based video processing applications with CAL

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