Gated-Clock Design of Linear-Feedback Shift Registers

Aloisi, W.; Mita, R.

doi:10.1109/tcsii.2007.914901

Cited by 37 publications

(27 citation statements)

References 13 publications

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“…Unlike [5] and [6], the resolution of gating proposed in this paper is of individual FFs at individual clock cycles. Gating at that resolution has been proposed for regularly structured circuits such as Linear feedback shift register (LFSR) [13] and counters [19], where the amount of power savings can be predicted from the circuit's structure. An attempt to discover an explicit clock disabling condition was made in [19].…”

Section: B Gated Clock Network Modelingmentioning

confidence: 99%

“…An implementation for a linear feedback shift register (LFSR) has been presented in [13], where a 10% net power reduction was reported. Additional power reduction can be achieved by lowering the number of clock gaters.…”

Section: Adaptive Clock Gating Implementationmentioning

confidence: 99%

“…An implementation of adaptive gating has been reported in [13], where, after taking into account the power consumed by the extra circuitry, a 10% net power savings was reported. We observed similar amounts of savings based on gate-level verilog simulations of designs, where adaptive gating was added to the first level of clock gater.…”

Section: Joint Gating and Gater's Optimal Fan-outmentioning

confidence: 99%

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The Optimal Fan-Out of Clock Network for Power Minimization by Adaptive Gating

Wimer

Koren

2012

IEEE Trans. VLSI Syst.

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Gating of the clock signal in VLSI chips is nowadays a mainstream design methodology for reducing switching power consumption. In this paper we develop a probabilistic model of the clock gating network that allows us to quantify the expected power savings and the implied overhead. Expressions for the power savings in a gated clock tree are presented and the optimal gater fan-out is derived, based on flip-flops toggling probabilities and process technology parameters. The resulting clock gating methodology achieves 10% savings of the total clock tree switching power. The timing implications of the proposed gating scheme are discussed. The grouping of FFs for a joint clocked gating is also discussed. The analysis and the results match the experimental data obtained for a 3-D graphics processor and a 16-bit microcontroller, both designed at 65-nanometer technology.

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Section: B Gated Clock Network Modelingmentioning

confidence: 99%

Section: Adaptive Clock Gating Implementationmentioning

confidence: 99%

Section: Joint Gating and Gater's Optimal Fan-outmentioning

confidence: 99%

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The Optimal Fan-Out of Clock Network for Power Minimization by Adaptive Gating

Wimer

Koren

2012

IEEE Trans. VLSI Syst.

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“…2 to be beneficial, the clock enabling signals of the grouped FFs should preferably be highly correlated. Data-driven clock gating is shown to achieve savings of more than 10% of the total dynamic power consumed by the clock tree [15]. Reference [24] reported 20% power savings.…”

Section: Data-driven Clock Gatingmentioning

confidence: 99%

Design Flow for Flip-Flop Grouping in Data-Driven Clock Gating

Wimer

Koren

2014

IEEE Trans. VLSI Syst.

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Abstract-Clock gating is a predominant technique used for power saving. It is observed that the commonly used synthesisbased gating still leaves a large amount of redundant clock pulses. Data-driven gating aims to disable these. To reduce the hardware overhead involved, flip-flops (FFs) are grouped so that they share a common clock enabling signal. The question of what is the group size maximizing the power savings is answered in a previous paper. Here we answer the question of which FFs should be placed in a group to maximize the power reduction. We propose a practical solution based on the toggling activity correlations of FFs and their physical position proximity constraints in the layout. Our data-driven clock gating is integrated into an Electronic Design Automation (EDA) commercial backend design flow, achieving total power reduction of 15%-20% for various types of large-scale state-of-the-art industrial and academic designs in 40 and 65 manometer process technologies. These savings are achieved on top of the savings obtained by clock gating synthesis performed by commercial EDA tools, and gating manually inserted into the register transfer level design.

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“…Because the switching activity of counter bits in a binary counter is decreased by half as the significance of each bit increases, this type of operation apparently causes a lot of redundant transitions, particularly for counter bits having Manuscript higher significance. Fine-grain clock-gating schemes [6], [7] can be used to eliminate these redundant transitions. Although these schemes can reduce some amount of power redundantly consumed, they typically require a large number of additional devices because extra logic gates are needed to generate a group of local gated clocks to define the triggering points of FFs.…”

Section: Introductionmentioning

confidence: 99%

Low-Power CMOS Synchronous Counter With Clock Gating Embedded Into Carry Propagation

Kim

et al. 2009

IEEE Trans. Circuits Syst. II

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A novel low-power CMOS synchronous counter whose clock-gating logic is embedded into a carry propagation circuit is proposed. The proposed synchronous counter operates with no redundant transitions and requires fewer transistors, minimizing the switching power consumption and silicon area as compared with conventional CMOS synchronous counters. The proposed synchronous counter consisting of 16 bits was fabricated in 0.18-μm CMOS technology. The experimental result indicates that the proposed synchronous counter achieves a power saving of 64% with 15% device count reduction.

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Gated-Clock Design of Linear-Feedback Shift Registers

Cited by 37 publications

References 13 publications

The Optimal Fan-Out of Clock Network for Power Minimization by Adaptive Gating

The Optimal Fan-Out of Clock Network for Power Minimization by Adaptive Gating

Design Flow for Flip-Flop Grouping in Data-Driven Clock Gating

Low-Power CMOS Synchronous Counter With Clock Gating Embedded Into Carry Propagation

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