Gated Clock and Revised Keeper (GCRK) Domino Logic Design in 16 nm CMOS Technology

Singhal, Smita; Mehra, Anu

doi:10.1080/03772063.2021.1875269

Cited by 5 publications

(3 citation statements)

References 9 publications

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“…Wide fan‐in circuits can be found in comparators, multiplexers, and microprocessor circuits 1 . The performance degradation is more obvious in other logic‐circuit families like pseudo‐NMOS due to the dc current of the always activated PMOS load 2 or dynamic CMOS logic due to the keeper‐contention current 3 . In this paper, a short discussion of the operation of CMOS circuits in the voltage, current, charge, and time domains is presented.…”

Section: Introductionmentioning

confidence: 99%

“…1 The performance degradation is more obvious in other logic-circuit families like pseudo-NMOS due to the dc current of the always activated PMOS load 2 or dynamic CMOS logic due to the keepercontention current. 3 In this paper, a short discussion of the operation of CMOS circuits in the voltage, current, charge, and time domains is presented. Then, the proposed time-mode scheme is presented and its performance superiority compared with the conventional CMOS logic-circuit families is verified for NAND and NOR gates with wide fan-in.…”

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confidence: 99%

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Proposed time‐mode wide fan‐in NAND and NOR gates

Sharroush

Badry

2023

Circuit Theory & Apps

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Summary CMOS circuits usually operate either in the voltage, current, charge, or time domain. Each of these domains has its own features. As the fan‐in of CMOS circuits increases, the performance of circuits that operate in the voltage domain, the current domain, or the charge domain degrades. This is the case especially with scaling down the power‐supply voltage associated with technology scaling. In this paper, a time‐mode scheme that utilizes a floating‐gate MOSFET (FGMOS) transistor is proposed. The proposed scheme showed good performance for wide fan‐in NAND and NOR gates. The design issues of the proposed scheme like the speed and the power consumption are investigated quantitatively. The performance of the proposed scheme is confirmed through simulation using the 45‐nm CMOS predictive technology model (PTM) with a 1‐V power‐supply voltage. 64‐input NAND and NOR gates realized using this scheme have time delays of 0.375 and 0.25 ns, respectively, at a load capacitance of 5 fF. The application of the proposed scheme for realizing multiplexers required in register files is illustrated and compared with the conventional domino logic in the superthreshold, near‐threshold, and subthreshold regions.

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Section: Introductionmentioning

confidence: 99%

mentioning

confidence: 99%

Proposed time‐mode wide fan‐in NAND and NOR gates

Sharroush

Badry

2023

Circuit Theory & Apps

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“…In [53], the contention current was eliminated at the beginning of the evaluation phase by modifying the keeper; specifically, an NMOS device was added in series to the keeper. In [54], a multiplexer was used for gating the clock signal, thus reducing the power consumption. Garg et al have proposed using the stack effect to reduce the noise effect and leakage currents, however at the cost of a delay penalty due to the addition of an inverter between the dynamic node and the output node [55].…”

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confidence: 99%

A Charge-Accumulation Based High-Performance CMOS Circuit

Sharroush

2022

Port-Said Engineering Research Journal

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There is no doubt that complementary metal-oxide semiconductor (CMOS) circuits with wide fan-in suffers from degraded performance. In this paper, a circuit that depends on charge accumulation is proposed as an alternative to conventional CMOS design. The proposed scheme is investigated quantitatively and verified by simulation using predictive technology model (PTM) of the 45 nm CMOS technology with a power-supply voltage, VDD, equal to 1 V. Although the proposed scheme suffers from more sensitivity to process variations compared to static CMOS, the comparative analysis and simulation results confirm the superiority of the proposed scheme from the points of view of speed, area, power consumption, and unity-noise gain. It is verified that the proposed scheme has a smaller area, power consumption, and delay compared to the conventional CMOS design when the number of inputs, n, exceeds four, two, and three, respectively. The impacts of process variations, component mismatches, and technology scaling are also investigated. The speed advantage gained from the proposed scheme is expected to be more obvious when operating in the subthreshold region. A figure of merit including the unity-noise gain, area, power consumption, and time delay is defined and the proposed scheme showed superior performance compared to the conventional CMOS logic when n exceeds four. Finally, the proposed scheme was compared with various previous schemes.

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Power Optimized Domino Logic Design of a Comparator with Variable Threshold CMOS and Clock Gating

Payyavula,

Reddy

2024

Lecture Notes in Electrical Engineering

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Gated Clock and Revised Keeper (GCRK) Domino Logic Design in 16 nm CMOS Technology

Cited by 5 publications

References 9 publications

Proposed time‐mode wide fan‐in NAND and NOR gates

Proposed time‐mode wide fan‐in NAND and NOR gates

A Charge-Accumulation Based High-Performance CMOS Circuit

Power Optimized Domino Logic Design of a Comparator with Variable Threshold CMOS and Clock Gating

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