Gate sizing for constrained delay/power/area optimization

Coudert, Olivier

doi:10.1109/92.645073

Cited by 122 publications

(90 citation statements)

References 24 publications

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“…A drawback of this approach, however, is that a potentially new critical path may emerge. This remains to be a major challenge for existing gate sizing techniques that attempt to maintain delay accuracy during optimization [9], [17], [18]. To address this issue, the frequency of delay updates can be increased by adjusting M and γ to be larger values, as we have done.…”

Section: Switching Activity Extraction Input Vector Controlmentioning

confidence: 99%

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Gate Sizing Under Uncertainty

Conos

Meguerdichian

Potkonjak

2015

IFIP Advances in Information and Communication Technology

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Abstract. We present a gate sizing approach to efficiently utilize gate switching activity (SA) and gate input vector control leakage (IVC) uncertainty factors in the objective function in order enable more efficient power and speed yield tradeoffs. Our algorithm conducts iterative gate freezing and unlocking with cut-based search for the most beneficial gate sizes under delay constraints. In an iterative flow, we interchangeably conduct gate sizing and IVC refinement to adapt to new circuit configurations. We evaluate our approach on benchmarks in 45 nm technology and demonstrate up to 62% (29% avg.) energy savings compared to a traditional objective function that does not consider SA and IVC. We further adapt our approach to optimize yield objectives by addressing processing variation (PV). Significant improvements were achieved under identical timing yield targets of up to 84% max (55% avg.) and 74% max (25% avg.) mean-power savings for selected ISCAS-85 and ITC-99 benchmarks, respectively.

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Section: Switching Activity Extraction Input Vector Controlmentioning

confidence: 99%

“…Several approaches exist that address continuous and discrete gate sizing. Common methods to solve the gate sizing problem have been convex optimization [4], Lagrangian Relaxation [2,3], [17], and gradient and sensitivity-based optimization [9], [18].…”

Section: Related Workmentioning

confidence: 99%

Gate Sizing Under Uncertainty

Conos

Meguerdichian

Potkonjak

2015

IFIP Advances in Information and Communication Technology

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“…It consists of substituting the big cells that are in the non-timing critical path by smaller gates that satisfy the delay requirement with identical logical function. Such a technique is widely used in the industry for timing, area [9,10], and power optimization [7,10].…”

Section: The Basic Concept Of Power Calculation and Optimizationmentioning

confidence: 99%

Evaluating the Impact of Max Transition Constraint Variations on Power Reduction Capabilities in Cell-Based Designs

Chentouf¹,

Ismaili

2017

JLPEA

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Abstract:Power optimization is a very important and challenging step in the physical design flow, and it is a critical success factor of an application-specific integrated circuit (ASIC) chip. Many techniques are used by the place and route (P&R) electronic design automation (EDA) tools to meet the power requirement. In this paper, we will evaluate, independently from the library file, the impact of redefining the max transition constraint (MTC) before the power optimization phase, and we will study the impact of over-constraining or under-constraining a design on power in order to find the best trade-off between design constraining and power optimization. Experimental results showed that power optimization depends on the applied MTC and that the MTC value corresponding to the best power reduction results is different from the default MTC. By using a new MTC definition method on several designs, we found that the power gain between the default methodology and the new one reaches 2.34%.

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Section: Technical Approachmentioning

confidence: 99%

Gate sizing in the presence of gate switching activity and input vector control

Conos

Meguerdichian

Potkonjak

2013

2013 IFIP/IEEE 21st International Conference on Very Large Scale Integration (VLSI-SoC)

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Abstract-We introduce a novel gate sizing approach that considers both the gate switching activity (SA) and gate input vector control leakage (IVC). We first extract SA using simulation and find promising input vectors. Next, in an iterative framework, we interchangeably conduct gate sizing and refining the IVC. As dictated by the new objective function, our algorithm conducts iterative gate freezing and unlocking with cut-based search for the most beneficial gate sizes under delay constraints. We evaluate our approach on standard benchmarks in 45 nm technology, showing promising improvement, achieving up to 62% (29% avg.) energy savings compared to the traditional objective function.

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Gate sizing for constrained delay/power/area optimization

Cited by 122 publications

References 24 publications

Gate Sizing Under Uncertainty

Gate Sizing Under Uncertainty

Evaluating the Impact of Max Transition Constraint Variations on Power Reduction Capabilities in Cell-Based Designs

Gate sizing in the presence of gate switching activity and input vector control

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