Gate oxide reliability on trapezoid-shaped defects and obtuse triangular defects in 4H-SiC epitaxial wafers

Abstract

The reliability of the gate oxide on large-area surface defects (trapezoid-shaped and obtuse triangular defects) in 4H-SiC epitaxial wafers is discussed. Time-dependent dielectric breakdown measurements revealed that a reduction in charge-to-breakdown (Q bd) occurred at a MOS capacitor including the downstream line of those defects. The deterioration of Q bd was at the same level in trapezoid-shaped defects and obtuse triangular defects. A cross-sectional transmission electron microscope (TEM) image and the simulation of the electric field distribution for the MOS structure indicated that the local fluctuation of the oxide thickness and/or the roughness of the interface on the downstream lines caused the degradation of the reliability of the MOS capacitors.

Analysis of Dislocation Structures in 4H‐SiC by Synchrotron X‐Ray Topography

“…It is further found that all these uneven structures on the epi‐wafer surface cause dielectric breakdowns of the MOS capacitors . Utilization of Berg–Barrett X‐ray topography, TEM, SEM, AFM, and optical microscope allowed us to understand the relationship between “various uneven structures on the epitaxy film surface” and “lattice defects in the epitaxy film resulting in unevenness” . Pits at the dislocation position were regarded as one of the significant factors of the MOS structure dielectric breakdowns on the 8°‐off substrate.…”

“…The cause of occurrence of the epitaxy film surface unevenness is related with the lattice defects in the epitaxy film in many cases. With the basal-plane dislocations with a relatively wide extension that exist in a bare wafer, stepbunchings are formed at the terminal ends on the surface due to the H 2 cleaning process before epitaxy film growth, which in some cases leads to the development of the surface unevenness by the epitaxy film growth process [38,39]. Uneven structures also occur at the terminal ends on the epitaxy film surface of the Frank-type stacking fault (called bar-shaped fault) [39,40].…”

“…Due to modification of the wafer off-angles and the epitaxy film growth technology in recent years, however, such dislocation pits are no longer a significant factor of the MOS structure dielectric breakdown, though they are still observed. Today, step-bunching on the epitaxy film surface and different uneven structures on the epitaxy film surface are the main causes of the MOS structure dielectric breakdowns [11,38]. Additionally, it is reported that the TDDB characteristic of the MOS capacitor is improved when the epitaxy film surface is smoothened by CMP and then thermally oxidized [42].…”

Chemical etching of silicon carbide in pure water by using platinum catalyst

“…However, the epitaxial growth induces surface waviness due to step bunching, which could significantly degrade the performance of the device. [5][6][7][8][9][10][11] The processing time was 3 min. Figures 6(a)-6(c) show the AFM images obtained over a 2 Â 2 lm 2 area of the pre-processed surface, and the surfaces processed at 2 and 3 min.…”

“…However, the performances of commercially available SiC devices are lower than their theoretical performances, owing to problems such as the non-uniform thickness of the oxide layer and killer defects. [5][6][7][8][9][10][11] One of the reasons for such fundamental problems is the flatness of the SiC substrate. To realize performances equal to the theoretical expectation for SiC devices, an atomically smooth surface without defects must be prepared.…”