Gate oxide reliability concerns in gate-metal sputtering deposition process: an effect of low-energy large-mass ion bombardment

Characteristics of TiO2Surfaces Etched by Capacitively Coupled Radio Frequency N2and He Plasmas

“…In order to prepare TiO 2 thin films, sputtering is one of the promising deposition techniques for uniform and large area coating [6][7][8]. However, plasma-induced damage of TiO 2 , which degrades the original characteristics, is a crucial problem because plasmas are used to sputter atoms from a target surface [9]. TiO 2 has also been expected for a candidate of gate dielectric material in metal-oxide-semiconductor transistors [10][11][12].…”

Effects of TiN Deposition on the Characteristics of W/TiN/SiO[sub 2]/Si Metal Oxide Semiconductor Capacitors

“…One approach to overcome these problems is to use a metal gate electrode deposited directly on the gate dielectrics. [2][3][4][5][6][7][8][9][10][11][12][13] A series of advanced researches on direct metal gates were carried out using W, 4 Mo, 5 WN x , 6 TiN x , 2,[6][7][8][9][10] and other metals on SiO 2 . [11][12][13] Buchanan et al reported W midgap metal gate compatible with ultrathin dielectric ͑ϳ3 nm͒ and demonstrated symmetric flatband voltages for n-and p-type substrate with a barrier height of 3.70 eV.…”

“…[2][3][4][5][6][7][8][9][10][11][12][13] A series of advanced researches on direct metal gates were carried out using W, 4 Mo, 5 WN x , 6 TiN x , 2,[6][7][8][9][10] and other metals on SiO 2 . [11][12][13] Buchanan et al reported W midgap metal gate compatible with ultrathin dielectric ͑ϳ3 nm͒ and demonstrated symmetric flatband voltages for n-and p-type substrate with a barrier height of 3.70 eV. 4 Some interesting results such as generation of interface traps and reliability degradation of MOS devices due to metal penetration and ion damage during the physical vapor deposition ͑PVD͒ process were presented.…”

“…4 Some interesting results such as generation of interface traps and reliability degradation of MOS devices due to metal penetration and ion damage during the physical vapor deposition ͑PVD͒ process were presented. 4,5,[10][11][12] To anneal the aforementioned defects, the MOS structures gated with direct metals were subjected to a post-metal anneal ͑PMA͒ at high temperatures or in a forming gas anneal ͑FGA͒. 4,5,[10][11][12] Most recently, the feasibility of W/TiN gate stack has been evaluated for conventional 130 nm CMOS technology and beyond.…”

“…4,5,[10][11][12] To anneal the aforementioned defects, the MOS structures gated with direct metals were subjected to a post-metal anneal ͑PMA͒ at high temperatures or in a forming gas anneal ͑FGA͒. 4,5,[10][11][12] Most recently, the feasibility of W/TiN gate stack has been evaluated for conventional 130 nm CMOS technology and beyond. 3,[7][8][9][10] W/TiN stack is of technological importance because of its midgap work function, low resistivity, and good diffusion barrier properties.…”