Proceedings 2002 Design, Automation and Test in Europe Conference and Exhibition
DOI: 10.1109/date.2002.998301
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Gate level fault diagnosis in scan-based BIST

Abstract: A gate level, automated fault diagnosis scheme is proposed for scan-based BIST designs. The proposed scheme utilizes both fault capturing scan chain information and failing test vector information and enables location identification of single stuck-at faults to a neighborhood of a few gates through set operations on small pass/fail dictionaries. The proposed scheme is applicable to multiple stuck-at faults and bridging faults as well. The practical applicability of the suggested ideas is confirmed through nume… Show more

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Cited by 10 publications
(7 citation statements)
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References 9 publications
(26 reference statements)
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“…In indirect diagnosis, the failing signatures are analyzed and the logic values captured by the scan elements are computed for each pattern in the pattern block. This procedure usually requires several test sessions [13], [14], [15], [16], [17], [18], [19]. Diagnosis algorithms for combinational logic can then be applied to the resulting failure information [20], [21], [22], [23].…”
Section: Built-in Diagnosismentioning
confidence: 99%
“…In indirect diagnosis, the failing signatures are analyzed and the logic values captured by the scan elements are computed for each pattern in the pattern block. This procedure usually requires several test sessions [13], [14], [15], [16], [17], [18], [19]. Diagnosis algorithms for combinational logic can then be applied to the resulting failure information [20], [21], [22], [23].…”
Section: Built-in Diagnosismentioning
confidence: 99%
“…The first group relies on the standard BIST architecture also referred to as STUMPS architecture [2]. The diagnosis methods proposed for this architecture are based on repeated test sessions, where the bandwidth necessary for the repetitions is not suitable for in-field scenarios and the test repetitions themselves already cause overhead in terms of test time [3], [4], [5], [6], [7]. The second diagnosis technique for random logic BIST relies on a dedicated hardware architecture [8].…”
Section: Introductionmentioning
confidence: 99%
“…The test sessions may target specific scan elements [3], [4], [5], [6], work on different pattern sets [7], or employ different response compactors [9], [10]. Once a set of faulty signatures is identified, logic diagnosis can proceed following one of two approaches.…”
Section: State Of the Artmentioning
confidence: 99%
“…The first group relies on the standard BIST architecture also referred to as STUMPS architecture [2]. The diagnosis methods proposed for this architecture are based on repeated test sessions, where the bandwidth necessary for the repetitions is not suitable for in-field scenarios and the test repetitions themselves already cause overhead in terms of test time [3], [4], [5], [6], [7]. The second diagnosis technique for random logic BIST relies on a dedicated hardware architecture [8].…”
Section: Introductionmentioning
confidence: 99%