Gate leakage properties in (Al2O3/HfO2/Al2O3) dielectric of MOS devices

Nasrallah, S. Abdi-Ben; Bouazra, A.; Poncet, A.; Saïd, M.

doi:10.1016/j.tsf.2008.08.047

Cited by 9 publications

(1 citation statement)

References 7 publications

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“…On the other hand, the Al 2 O 3 is the superior candidate to replace the SiO 2 layer because of the similar energy band offset, the controllability of thin thickness and possibility of low temperature process. 11) Therefore, in this paper, we fabricated the asymmetrical VARIOT tunnel barriers with various HfO 2 thicknesses stacked on ultrathin SiO 2 or Al 2 O 3 layers and investigated the tunneling current and charge trapping characteristics. Especially, the thickness effects of HfO 2 layer were studied to determine the application of either a tunnel barrier or a charge trapping layer for high performance nonvolatile memories.…”

Section: Introductionmentioning

confidence: 99%

Charge Trapping Characteristics of Variable Oxide Thickness Tunnel Barrier with SiO₂/HfO₂ or Al₂O₃/HfO₂ Stacks for Nonvolatile Memories

Kim

Jung

Park

et al. 2009

jjap

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Charge trapping characteristics of asymmetrical tunnel barriers consisting of different dielectric materials were investigated for application of nonvolatile memory devices. A thin HfO 2 layer stacked on ultrathin SiO 2 layer (SiO 2 /HfO 2 tunnel barrier) revealed higher current sensitivity to applied gate voltage than the conventional single SiO 2 tunnel barrier. On the other hand, the electron trapping of the tunnel barriers increased with the thickness of HfO 2 layer. Thus, a thin HfO 2 layer is promising for the engineered tunnel barriers, while a thick HfO 2 layer is appropriate for charge trapping layers for high-integrated nonvolatile memories. Meanwhile, an ultrathin Al 2 O 3 /HfO 2 tunnel barrier also revealed good electrical characteristics and is suitable for low temperature fabrication process.

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Section: Introductionmentioning

confidence: 99%

Charge Trapping Characteristics of Variable Oxide Thickness Tunnel Barrier with SiO₂/HfO₂ or Al₂O₃/HfO₂ Stacks for Nonvolatile Memories

Kim

Jung

Park

et al. 2009

jjap

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Effects of post deposition annealing, interface states and series resistance on electrical characteristics of HfO2 MOS capacitors

Kahraman

Yılmaz

Kaya³

et al. 2015

J Mater Sci: Mater Electron

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The purposes of this paper are to investigate the post deposition annealing (PDA) effect on structural and electrical characterizations of HfO 2 MOS capacitor and the frequency dependency of series resistance and interface states in this device. PDA processes on the HfO 2 films deposited using RF magnetron sputtering system were performed in N 2 ambient at 350, 550, 650, and 750°C. The phase identifications and crystallization degrees of the HfO 2 films were determined by using X-ray diffractometry. The grain size of the films was varied from 4.5 to 15.23 with increasing in PDA temperature. The HfO 2 MOS capacitors were fabricated using the as-deposited and annealed films for electrical characterization. C-V and G/ x-V measurements were performed at 1 MHz frequency. The C-V characteristics of the MOS capacitor fabricated with film annealed at 550°C show a better behaviour in terms of the high dielectric constant and low effective oxide charge compared to others. For this device, C-V and G/x-V measurements were performed in different frequencies ranging from 10 kHz to 1 MHz at room temperature. Obtained results show that series resistance and interface states strongly influence the C-V and G/x-V behaviour of the MOS capacitor.

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Transparent multi-level-cell nonvolatile memory with dual-gate amorphous indium-gallium-zinc oxide thin-film transistors

Ahn

Cho

2016

Applied Physics Letters

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A fully transparent, nonvolatile charge-trap-flash memory that is based on amorphous indium-gallium-zinc-oxide thin film transistors was fabricated with a dual gate (DG) structure for a multi-level-cell (MLC) application. A large memory window was obtained at a low program voltage in the DG read-operation mode owing to the capacitive-coupling effect between the front gate and the back gate. The MLC was implemented by using the DG read-operation mode with four highly stable levels, as follows: A large threshold-voltage difference >3.5 V per level was obtained under a low program voltage <14 V with a fast program speed of 1 ms. In contrast, the conventional single gate operation mode was incompatible with the MLC application.

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Gate leakage properties in (Al2O3/HfO2/Al2O3) dielectric of MOS devices

Cited by 9 publications

References 7 publications

Charge Trapping Characteristics of Variable Oxide Thickness Tunnel Barrier with SiO₂/HfO₂ or Al₂O₃/HfO₂ Stacks for Nonvolatile Memories

Charge Trapping Characteristics of Variable Oxide Thickness Tunnel Barrier with SiO₂/HfO₂ or Al₂O₃/HfO₂ Stacks for Nonvolatile Memories

Effects of post deposition annealing, interface states and series resistance on electrical characteristics of HfO2 MOS capacitors

Transparent multi-level-cell nonvolatile memory with dual-gate amorphous indium-gallium-zinc oxide thin-film transistors

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Gate leakage properties in (Al2O3/HfO2/Al2O3) dielectric of MOS devices

Cited by 9 publications

References 7 publications

Charge Trapping Characteristics of Variable Oxide Thickness Tunnel Barrier with SiO2/HfO2 or Al2O3/HfO2 Stacks for Nonvolatile Memories

Charge Trapping Characteristics of Variable Oxide Thickness Tunnel Barrier with SiO2/HfO2 or Al2O3/HfO2 Stacks for Nonvolatile Memories

Effects of post deposition annealing, interface states and series resistance on electrical characteristics of HfO2 MOS capacitors

Transparent multi-level-cell nonvolatile memory with dual-gate amorphous indium-gallium-zinc oxide thin-film transistors

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Product

Resources

About

Charge Trapping Characteristics of Variable Oxide Thickness Tunnel Barrier with SiO₂/HfO₂ or Al₂O₃/HfO₂ Stacks for Nonvolatile Memories

Charge Trapping Characteristics of Variable Oxide Thickness Tunnel Barrier with SiO₂/HfO₂ or Al₂O₃/HfO₂ Stacks for Nonvolatile Memories