Gate Disturb Reduction in a Silicon Nanocrystal Flash EEPROM by Means of Natural Threshold Voltage Reduction

Abstract

IntroductionAs CMOS technology is scaled to the 90nm node and beyond, silicon nanocrystal nonvolatile memories are receiving increased attention as a replacement for floating gate nonvolatile memories [1,2]. The thin dielectrics in these memories can lead to excessive gate disturb during the read operation. Of primary concern is the loss of electrons of the program state to the gate through the top oxide overlying the nanocrystals. This loss is the result of tunneling due to the high electric field between the gate and the nanocrystals. It has been shown that reducing the natural threshold voltage (V t,nat ) of the memory cell leads to a reduction in gate disturb [3]. Simple reduction of the V t,nat by decreasing the substrate doping concentration can result in severely degraded short channel performance, as well as degraded hot carrier injection (HCI) performance during the program operation. Thus, it is desired to construct a substrate doping profile with a light surface concentration to obtain a low V t,nat , and a heavy doping concentration just below the surface to provide robust short channel performance and good HCI programmability.

Integration of CVD silicon nanocrystals in a 32Mb NOR flash memory

“…Due to the relatively thin active dielectrics [8], gate disturb issues is one of the major concerns of Si-NC memories. During read operation of programmed cells, a positive bias is applied to the control gate.…”

“…We use a simple analytical model described in Ref. [8], where the programming window formula is linked to the dot density and dot size through a compound distribution theory. Using information coming from TEM inspections on the dot size distribution of different samples, we were able to calculate the standard deviation of programming window in the case of a completely random distribution of dot nucleation (Poisson distribution, Fano factor = 1) and in the case of a more organised configuration (Fano factor < 1) [9].…”

“…Nevertheless, it should be stated that to date, the promising performances of Si-NC memories have been mainly demonstrated on single cells or medium-sized arrays (1)(2)(3)(4)(5)(6)(7)(8)(9)(10)(11)(12)(13)(14)(15)(16) [1][2][3][4][5][6]. An extensive set of experiments, including performance and reliability data of large-scale integrated memories should still be provided.…”

Materials Challenges in Automotive Embedded Non-Volatile Memories

“…Silicon nanocrystals are manufacturable in a standard rapid thermal chemical vapor deposition (RT-CVD) tool, as shown in Figure 15. The nanocrystal bitcell parameters have to be optimized to minimize undesired charge loss [7]. Instead, silicon atoms attach to already present nuclei resulting in their further growth.…”