Gate-All-Around technology: taking advantage of ballistic transport ?

Bidal, G.; Huguenin, J.-L.; Denorme, S.; Fleury, Dominique; Loubet, N.; Pouydebasque, A.; Perreau, P.; Leverd, F.; Barnola, S.; Beneyton, R.; Orlando, B.; Gouraud, P.; Salvetat, T.; Clement, L.; Monfray, S.; Ghibaudo, G.; Bœuf, F.; Skotnicki, T.

doi:10.1109/essderc.2009.5331466

Cited by 4 publications

(5 citation statements)

References 3 publications

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“…Silicon nanowire (SiNW) FETs have the most effective channel controllability and nearly ideal off-characteristics have been experimentally demonstrated [1]. I ON enhancement of the SiNW FET has also been reported [2]. Higher I ON with lower I OFF is advantageous for realization of a low power supply voltage device and thus a low power consumption device application.…”

Section: Introductionmentioning

confidence: 99%

Structural advantages of rectangular-like channel cross-section on electrical characteristics of silicon nanowire field-effect transistors

Sato

Kakushima²,

Ahmet

et al. 2011

Microelectronics Reliability

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We have experimentally demonstrated structural advantages due to rounded corners of rectangular-like cross-section of silicon nanowire (SiNW) field-effect transistors (FETs) on on-current (I ON), inversion charge density normalized by a peripheral length of channel cross-section (Q inv) and effective carrier mobility ( eff). The I ON was evaluated at the overdrive voltage (V OV) of 1.0 V, which is the difference between gate voltage (V g) and the threshold voltage (V th), and at the drain voltage of 1.0 V. The SiNW nFETs have revealed high I ON of 1600 A/m of the channel width (w NW) of 19 nm and height (h NW) of 12 nm with the gate length (L g) of 65 nm. We have separated the amount of on-current per wire at V OV = 1.0 V to a corner component and a flat surface component, and the contribution of the corners was nearly 60 % of the total I ON of the SiNW nFET with L g of 65 nm. Higher Q inv at V OV = 1.0 V evaluated by advanced split-CV method was obtained with narrower SiNW FET, and it has been revealed the amount of inversion charge near corners occupied 50 % of all the amount of inversion charge of the SiNW FET (w NW = 19 nm and h NW = 12 nm). We also obtained high  eff of the SiNW FETs compared with that of SOI planar nFETs. The  eff at the corners of SiNW FET has been calculated with the separated amount of inversion charge and drain conductance. Higher  eff around corners is obtained than the original  eff of the SiNW nFETs. The higher  eff and the large fractions of I ON and Q inv around the corners indicate that the rounded corners of rectangular-like cross-sections play important roles on the enhancement of the electrical performance of the SiNW nFETs.

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Section: Introductionmentioning

confidence: 99%

Structural advantages of rectangular-like channel cross-section on electrical characteristics of silicon nanowire field-effect transistors

Sato

Kakushima²,

Ahmet

et al. 2011

Microelectronics Reliability

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“…In 1999, Huang et al [8] demonstrated the first FinFET with a gate length L G of sub-50 nm and a fin width of 15− 30 nm. Following that, leading research groups and foundries like IBM [11] , STMicroelectronics [15] , Intel [5,10] , TSMC [16,27] , Samsung [17] . IME [18] , etc.…”

Section: Process Development Of Si Multi-gate Transistors 21 a Histor...mentioning

confidence: 99%

“…(a-f) Schematics of MuGFETs with different gate geometries: (a) IMEC's gate-all-around (GAA) MOSFET [14] , (b) the world-first FinFET [8] , (c) IBM's double-gate (DG) FinFET [11] , (d) STMicroelectronics's GAA MOSFET [15] , (e) Intel's tri-gate FinFET [10] , (f) TSMC's nanowire FinFET [16] . (g-i) TEM images showing the cross-sectional view of fins/nanowires from early works: (g) IBM's DG FinFET [11] , (h) Intel's tri-gate FinFET [10] , (i) Samsung's nanowire MOSFET [17] , (j) IME's nanowire GAA MOSFET [18] , (k) TSMC's FinFET [27] , (l) STMicroelectronics's GAA MOSFET [28] . ferent process technology, namely, bulk planar FETs, fully-depleted SOI (FDSOI) FETs, and FinFETs [29] .…”

Section: Process Development Of Si Multi-gate Transistors 21 a Histor...mentioning

confidence: 99%

“…At similar gate length, planar transistors (in black) exhibit much larger DIBL than the MuGFETs, indicating poor control of SCEs. Although FDSOI transistors could also be used for excellent SCE suppression, the current per footprint is lower than FinFETs [27,37] , and what's more, the 3D stacked NS MuGFETs [19] , as the latter two technologies utilize the advantage of vertical dimension for carrier transport.…”

Section: Process Challenges In State-of-the-art Mugfetsmentioning

confidence: 99%

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The past and future of multi-gate field-effect transistors: Process challenges and reliability issues

Sun

Zhang

et al. 2021

J. Semicond.

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This work reviews the state-of-the art multi-gate field-effect transistor (MuGFET) process technologies and compares the device performance and reliability characteristics of the MuGFETs with the planar Si CMOS devices. Owing to the 3D wrapped gate structure, MuGFETs can suppress the SCEs and improve the ON-current performance due to the volume inversion of the channel region. As the Si CMOS technology pioneers to sub-10 nm nodes, the process challenges in terms of lithography capability, process integration controversies, performance variability etc. were also discussed in this work. Due to the severe self-heating effect in the MuGFETs, the ballistic transport and reliability characteristics were investigated. Future alternatives for the current Si MuGFET technology were discussed at the end of the paper. More work needs to be done to realize novel high mobility channel MuGFETs with better performance and reliability.

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“…Therefore, smoothing technologies, such as hydrogen annealing [7] and hydrogen thermal etching [8], have also been proposed for rounding the SiNW channel or etching the LER of the SiNW channel. As a result, there exist various cross-sectional shapes of the SiNW channels: triangular [2,4], circular [1], ellipsoidal [9], and rectangular [10]. The effects of the various cross-sectional shapes of the SiNW FETs on their electrical properties have been reported, for example, the gate capacitance [11], the on-current I ON [12], the threshold voltage (V th ) [13], the effective carrier mobility (µ eff ) [14], and the interfacial state density (D it ) [15].…”

Section: Introductionmentioning

confidence: 99%

Effects of corner angle of trapezoidal and triangular channel cross-sections on electrical performance of silicon nanowire field-effect transistors with semi gate-around structure

Sato

Kakushima

Ahmet

et al. 2011

Solid-State Electronics

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Structural effects, especially corner angle of upper-corners of trapezoidal and rectangular, and triangular cross-sectional shapes of silicon nanowire field-effect transistors on effective carrier mobility and normalized inversion charge density have been investigated. <100>-directed silicon nanowire field-effect transistors with semi-gate around structure fabricated on (100)-oriented silicon-on-insulator wafers were evaluated. As the upper-corner angle decreased from obtuse to acute angle, we observed an increased amount of inversion charge using split-CV measurement. On the other hand, the effective carrier mobility dependence on the upper-corner angle seems to have an optimized point near 100 o at 296 K. Although normalized inversion charge density was the largest with acute angles, effective carrier mobility with acute upper-corner angle was severely degraded.Considering the intrinsic delay time of SiNW FET, SiNW FETs with trapezoidal cross-section with upper-corner angle of 100 o is more suitable in this work to achieve high electrical performance. We believe these findings could represent guidelines for the design of high-performance SiNW FETs.

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Gate-All-Around technology: taking advantage of ballistic transport ?

Cited by 4 publications

References 3 publications

Structural advantages of rectangular-like channel cross-section on electrical characteristics of silicon nanowire field-effect transistors

Structural advantages of rectangular-like channel cross-section on electrical characteristics of silicon nanowire field-effect transistors

The past and future of multi-gate field-effect transistors: Process challenges and reliability issues

Effects of corner angle of trapezoidal and triangular channel cross-sections on electrical performance of silicon nanowire field-effect transistors with semi gate-around structure

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