Gate-all-around MOSFETs: lateral ultra-narrow (≤10 nm) fin as channel body

Technology CAD of Nanowire FinFETs

“…Low drain-induced barrier lowering (DIBL) of ~10 mV/V is obtained, with I ON /I OFF > 10 7 at room temperature. These results are similar to those reported for nanowire Ω-FinFETs by Singh et al (Singh et al, 2005). Fig.…”

“…To activate the mobility model appropriate mobility values were defined in the fields of the parameter file. Simulation data for the drain current (I ds ) versus gate voltage (Vgs) curves match the experimentally measured results very well (Singh et al, 2005). Fig.…”

Random Telegraph Signal Noise in Gate-All-Around Si-FinFET With Ultranarrow Body

“…The active areas were patterned and etched down to the BOX to make fins with desired critical dimension (width of ∼ 70 nm and length of ∼ 100-500 nm), which was then oxidized in dry O 2 (875 • C/5 hr), resulting in a Si core forming the FinFET channel. Further details of the device fabrication have been reported elsewhere [4]. TEM imaging of our devices [4] shows a silicon fin with height of 100 nm and width of 10 nm.…”

“…Further details of the device fabrication have been reported elsewhere [4]. TEM imaging of our devices [4] shows a silicon fin with height of 100 nm and width of 10 nm. For calculation purposes, we treat the device as a double lateral channel FinFET with W ∼ 100 nm (fin height) since the top and bottom gates are too narrow to have a significant contribution.…”

Hot carrier degradation in nanowire (NW) FinFETs

“…The process flow used in this work is similar to the process flow reported by Singh et al [4,5]. The starting material is an SOI wafer with a top silicon layer (p-type, ~10 15 /cm 3 ) thickness of 200-nm over a 150-nm BOX.…”