Garp: a MIPS processor with a reconfigurable coprocessor

Hauser, John R.; Wawrzynek, John

doi:10.1109/fpga.1997.624600

Cited by 529 publications

(306 citation statements)

References 10 publications

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“…However, for this paper we fix the ALU data width to be 32-bits. Our approach differs from GARP [8] insomuch as we tailor the hardware co-processor to the application domain. Compared to RaPiD [4], which has smaller RAMs and registers to store data and intermediate results, our fabric is purely combinational.…”

Section: Acceleration With Custom Hardwarementioning

confidence: 99%

Interconnect Customization for a Coarse-grained Reconfigurable Fabric

Mehta

Slander

Baz

et al. 2007

2007 IEEE International Parallel and Distributed Processing Symposium

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This paper describes several system-level interconnection strategies for a coarse-grained reconfigurable fabric designed for low-energy hardware acceleration. A small, representative sub-graph for signal and image processing applications is used to predict the success of mapping larger applications onto the fabric device with these different interconnection strategies, which include 32:1, 8:1, 5:1, 4:1, 3553:1 (3:1, 5:1, 5:1, 3:1) and 355:1 (3:1, 5:1, 5:1) cardinalities. Three mapping techniques are presented and used to complete mappings onto several of these fabric instances including a mixed integer linear programming technique, a constraint programming approach, and a greedy heuristic. We present results for area (in number of required rows), power, delay, and energy as well as run times for mapping a set of signal and image processing benchmarks onto each of these interconnects. Our results indicate that the 5:1 interconnect provides the best overall results and does not require any additional hardware resources than the baseline 4:1 technique. When compared with other implementation strategies, the reconfigurable fabric energy consumption, using 5:1-based interconnect, is within 5-10X of a direct ASIC implementation, is 10X better than an Virtex II Pro FPGA and is 100X better than an Intel XScale processor.

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Section: Acceleration With Custom Hardwarementioning

confidence: 99%

Interconnect Customization for a Coarse-grained Reconfigurable Fabric

Mehta

Slander

Baz

et al. 2007

2007 IEEE International Parallel and Distributed Processing Symposium

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“…Amalgam builds on this success with the addition of reconfigurable logic in the form of reconfigurable clusters. The integration of programmable and reconfigurable logic has been attempted in Garp [9] and Chimaera [18]. The rowbased design of the reconfigurable cluster is based heavily off of the architecture of Garp.…”

Section: Related Workmentioning

confidence: 99%

A reconfigurable unit for a clustered programmable-reconfigurable processor

Kujoth

Wang

Gottlieb

et al. 2004

Proceedings of the 2004 ACM/SIGDA 12th International Symposium on Field Programmable Gate Arrays

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In a clustered programmable-reconfigurable processor, multiple programmable processors and blocks of reconfigurable logic communicate through a register-based communication mechanism, which reduces the impact of wire delay on clock cycle time. In this paper, we present a circuit-level design for the reconfigurable clusters used on the Amalgam programmable-reconfigurable processor. We outline our interleaved reconfigurable array design, which provides high bandwidth to and from the register file without requiring large amounts of register control logic. We characterize the latency of operations in our array, and present results that show the impact that this latency has on overall system performance in a range of fabrication processes. Finally, we present a pipelining scheme that enables the array to operate at clock rates closer to those of programmable processors and allows for better scaling in future technologies.

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“…In addition to the MMX technology, where new ISAs are added in the general processor to speed up the multimedia operation, recently, some processor architectures have been proposed to provide multiple configuration contexts in chip to program the LUTs and crossbars, like DPGA [1], or incorporate the general purpose processor with reconfigurable computing unit, such as GARP [2], MATRIX [3], RaPiD [4], RAW [5]. Basically, this kind of new architecture can be sub-divided into two categories: 1) Fine-grained level reconfigurable unit, such as FPGA.…”

Section: Introductionmentioning

confidence: 99%

MorphoSys: a reconfigurable processor targeted to high performance image application

Lee

Singh

et al. 1999

Lecture Notes in Computer Science

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This paper addresses the design idea of the MorphoSys Reconfigurable processor developed by the researchers in the UC, Irvine. With the demand to perform the multimedia operations efficiently, it is one of the directions that general processor needs to incorporate with some reconfigurable computing units, like FPGA. In MorphoSys project, we successfully propose a prototype to fulfill the above trend, which is comprised of a simplified general purpose MIPS-like RISC processor, called TinyRISC and 8x8 coarse grained reconfigurable cells, organized as SIMD architecture. MorphoSys is realized using 0.35um technology, and runs at 100Mhz with impressive performance enhancement compared with other architectures.

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Garp: a MIPS processor with a reconfigurable coprocessor

Cited by 529 publications

References 10 publications

Interconnect Customization for a Coarse-grained Reconfigurable Fabric

Interconnect Customization for a Coarse-grained Reconfigurable Fabric

A reconfigurable unit for a clustered programmable-reconfigurable processor

MorphoSys: a reconfigurable processor targeted to high performance image application

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