MorphoSys: a reconfigurable processor targeted to high performance image application

Lu, Guangming; Lee, Ming-Hau; Singh, Hartej; Bagherzadeh, Nader; Kurdahi, Fadi; Filho, E.M.C.

doi:10.1007/bfb0097951

Cited by 6 publications

(7 citation statements)

References 10 publications

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“…As an alternative coarse grained reconfigurable hardware architectures that allow faster context loading compared to fine grained FPGA architectures with large bitstream size [2,3] were presented. However, due to limited reconfigurable resources, these devices are lack of providing massive parallelism.…”

Section: Context Loadingmentioning

confidence: 99%

“…Therefore, these devices were not suitable for reconfigurable computing platforms requiring the hardware to be changed frequently. Hence, some coarse grained reconfigurable hardware architectures (like, MorphoSys [2] and Chimera [3]) are proposed. These devices are configured in very short time.…”

Section: Introductionmentioning

confidence: 99%

“…On the other hand, with large number of logical resources and massive parallelism features, the first generations of FPGA were useful as a co-processor to accelerate part of an application and 10 to 100 times performance was achieved in terms of execution time. The literature includes a number of case studies that demonstrate such performance gain [2][3][4][5][6][7].…”

Section: Introductionmentioning

confidence: 99%

See 2 more Smart Citations

A reconfigurable computing platform for real time embedded applications

Say

Bazlamaçcı

2012

Microprocessors and Microsystems

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, 136 pages Today's reconfigurable devices successfully combine 'reconfigurable computing machine' paradigm and 'high degree of parallelism' and hence reconfigurable computing emerged as a promising alternative for computing-intensive applications. Despite its superior performance and lower power consumption compared to general purpose computing using microprocessors, reconfigurable computing comes with a cost of design complexity. This thesis aims to reduce this complexity by providing a flexible and user friendly development environment to application programmers in the form of a complete reconfigurable computing platform. ACKNOWLEDGMENTS First, I must thank my advisor, Assoc. Prof. Dr. Cüneyt Fehmi Bazlamaçcı for his support during both my MSc and PhD studies. This work would not have been possible without his guidance, advice, criticism and encouragements. I would also like to express my gratitude to my dissertation committee members; Prof. Dr. Hasan Cengiz Güran and Prof. Dr. Volkan Atalay. They have provided many useful insights and helpful feedback during this process. I would like to acknowledge my company ASELSAN Inc. for the encouragement and support during my MSc and PhD studies. Last but not the least, I must thank my wife,Şifa Say, whose love and support are crucial for anything I have ever accomplished. I also thank our kids, Eren and Berra for bringing me sunshine and happiness.

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Section: Context Loadingmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

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A reconfigurable computing platform for real time embedded applications

Say

Bazlamaçcı

2012

Microprocessors and Microsystems

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“…International Journal of Reconfigurable Computing 5 2@1 3@1 4@1 5@1 2@2 3@2 4@2 5@2 6@2 7@2 1@3 2@3 3@3 4@3 5@3 6@3 7@3 1@4 2@4 3@4 4@4 5@4 6@4 7@4 1@5 2@5 3@5 4@5 5@5 6@5 7@5 1@6 2@6 3@6 4@6 5@6 6@6 3@7 4@7 5@7 6@7 Architectures presented are Kress-Array [13], Piperench [14], PACT XPP [15], and Morphosys [16]. Programming model issues are discussed with a comparison between software oriented approach (generally using subsets of C) and hardware approach (netlist based descriptions).…”

Section: Reconfigurable Rfu Designmentioning

confidence: 99%

Experiment Centric Teaching for Reconfigurable Processors

Lagadec

Picard

Corre

et al. 2011

International Journal of Reconfigurable Computing

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This paper presents a setup for teaching configware to master students. Our approach focuses on experiment and leaning-by-doing while being supported by research activity. The central project we submit to students addresses building up a simple RISC processor, that supports an extensible instructions set thanks to its reconfigurable functional unit. The originality comes from that the students make use of the Biniou framework. Biniou is a research tool which approach covers tasks ranging from describing the RFU, synthesizing it as VHDL code, and implementing applications over it. Once done, students exhibit a deep understanding of the domain, ensuring the ability to fast adapt to state-of-the-art techniques.

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“…REMARC [21] and MorphoSys [19] are two designs that also proposed computation architectures more suited for computation of DFG primitives than an FPGA. These coprocessors were geared toward large blocks in multimedia applications, as compared to our design, which executes smaller blocks of computation.…”

Section: Related Workmentioning

confidence: 99%

Application-Specific Processing on a General-Purpose Core via Transparent Instruction Set Customization

Clark

Kudlur

Park

et al.

37th International Symposium on Microarchitecture (MICRO-37'04)

153

115

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Application-specific instruction set extensions are an effective way of improving the performance of processors. Critical computation subgraphs can be accelerated by collapsing them into new instructions that are executed on specialized function units. Collapsing the subgraphs simultaneously reduces the length of computation as well as the number of intermediate results stored in the register file. The main problem with this approach is that a new processor must be generated for each application domain. While new instructions can be designed automatically, there is a substantial amount of engineering cost incurred to verify and to implement the final custom processor. In this work, we propose a strategy to transparent customization of the core computation capabilities of the processor without changing its instruction set. A configurable array of function units is added to the baseline processor that enables the acceleration of a wide range of dataflow subgraphs. To exploit the array, the microarchitecture performs subgraph identification at run-time, replacing them with new microcode instructions to configure and utilize the array. We compare the effectiveness of replacing subgraphs in the fill unit of a trace cache versus using a translation table during decode, and evaluate the tradeoffs between static and dynamic identification of subgraphs for instruction set customization.

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MorphoSys: a reconfigurable processor targeted to high performance image application

Cited by 6 publications

References 10 publications

A reconfigurable computing platform for real time embedded applications

A reconfigurable computing platform for real time embedded applications

Experiment Centric Teaching for Reconfigurable Processors

Application-Specific Processing on a General-Purpose Core via Transparent Instruction Set Customization

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