1997
DOI: 10.1016/s0167-9317(96)00028-7
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Gap filling with PVD processes for copper metallized integrated circuits

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Cited by 10 publications
(3 citation statements)
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“…Thus Cu interconnects, combined with low- k materials, offer better chip performance, higher reliability, and lower power consumption compared to Al interconnects in silicon-based semiconductors. Current Cu film deposition technologies are either vacuum-based methods such as physical vapor deposition (PVD) and chemical vapor deposition (CVD), or solution-based methods such as electroless deposition and electrodeposition. Although highly pure Cu films can be deposited, Cu PVD is often considered to be unsuitable for Cu damascene process. This is because Cu PVD often results in poor gap filling and conformity and creation of a void when depositing high-aspect-ratio features . Utilization of Cu CVD in industry is limited by the requirement of high volatility of organocopper compounds, high deposition temperature (>200 °C), possible incorporation of impurities into the film, complexity of CVD processes, and high tool cost.…”
Section: Introductionmentioning
confidence: 99%
“…Thus Cu interconnects, combined with low- k materials, offer better chip performance, higher reliability, and lower power consumption compared to Al interconnects in silicon-based semiconductors. Current Cu film deposition technologies are either vacuum-based methods such as physical vapor deposition (PVD) and chemical vapor deposition (CVD), or solution-based methods such as electroless deposition and electrodeposition. Although highly pure Cu films can be deposited, Cu PVD is often considered to be unsuitable for Cu damascene process. This is because Cu PVD often results in poor gap filling and conformity and creation of a void when depositing high-aspect-ratio features . Utilization of Cu CVD in industry is limited by the requirement of high volatility of organocopper compounds, high deposition temperature (>200 °C), possible incorporation of impurities into the film, complexity of CVD processes, and high tool cost.…”
Section: Introductionmentioning
confidence: 99%
“…For conventional silicon integrated circuit technology, as the integration level is increased, the resulting reduced feature sizes require the ability to fill the interconnect metal into high aspect ratio holes, generally about 10:1. 5 Both chemical vapor deposition 6-8 ͑CVD͒ and physical vapor deposition 9 have been used successfully for this application. Researchers are also applying atomic layer deposition systems for the conformal coating of sub-100-nm level high aspect ratio structures which have shown a filling of about 40:1 aspect ratio.…”
Section: Introductionmentioning
confidence: 99%
“…1 Therefore, there continues to be a growing need for conformal coating in the microelectronics industry. In the area of microelectronics, a search is underway to find a reliable technique for filling trenches and vias using copper-metallization technology.…”
Section: Introductionmentioning
confidence: 99%