GANGLION-a fast hardware implementation of a connectionist classifier

Cox, Charles E.; Blanz, W. E.

doi:10.1109/cicc.1991.164044

Cited by 20 publications

(4 citation statements)

References 2 publications

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“…As mentioned previously, a fully-or semi-parallel VLSI implementation of DBN in binary form requires a lot of hardware resources. Therefore, many works target FPGAs [30]- [35], but none manage to fit a fully-parallel deep neural network architecture in a single FPGA board. Recently, a fully pipelined FPGA architecture of a factored RBM (fRBM) was proposed in [9], which could implement a single layer neural network consisting of 4096 nodes using virtualization technique, i.e., time multiplex sharing technique, on a Virtex-6 FPGA board.…”

Section: B Fpga Implementationmentioning

confidence: 99%

VLSI Implementation of Deep Neural Network Using Integral Stochastic Computing

Ardakani

Leduc-Primeau

Onizawa

et al. 2017

IEEE Trans. VLSI Syst.

208

102

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The hardware implementation of deep neural networks (DNNs) has recently received tremendous attention: many applications in fact require high-speed operations that suit a hardware implementation. However, numerous elements and complex interconnections are usually required, leading to a large area occupation and copious power consumption. Stochastic computing has shown promising results for low-power area-efficient hardware implementations, even though existing stochastic algorithms require long streams that cause long latencies. In this paper, we propose an integer form of stochastic computation and introduce some elementary circuits. We then propose an efficient implementation of a DNN based on integral stochastic computing. The proposed architecture has been implemented on a Virtex7 FPGA, resulting in 45% and 62% average reductions in area and latency compared to the best reported architecture in literature. We also synthesize the circuits in a 65 nm CMOS technology and we show that the proposed integral stochastic architecture results in up to 21% reduction in energy consumption compared to the binary radix implementation at the same misclassification rate. Due to fault-tolerant nature of stochastic architectures, we also consider a quasi-synchronous implementation which yields 33% reduction in energy consumption w.r.t. the binary radix implementation without any compromise on performance.

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Section: B Fpga Implementationmentioning

confidence: 99%

VLSI Implementation of Deep Neural Network Using Integral Stochastic Computing

Ardakani

Leduc-Primeau

Onizawa

et al. 2017

IEEE Trans. VLSI Syst.

208

102

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“…This approach begins by training a neural network to model the circuit under design. As described in Section II-A, the weights of the neural network are adjusted at this stage to minimize its error function given by (3). The solution searching is then performed by applying a modified backpropagation learning rule to the trained network.…”

Section: Design By a Neural Network Learning Processmentioning

confidence: 99%

“…A software implementation of a neural network is sluggish since the neurons have to be updated sequentially. Only hardware implementations, which explore the parallelism of neural network computing, can fully realize its potential [2], [3]. In prior efforts at applying neural network models in microwave design, while the neural network training and modeling operations could be accelerated by a neural network processor, the solution-searching optimization (e.g., a gradient method) remained as a software routine external to the neural network model.…”

Section: Introductionmentioning

confidence: 99%

Reverse modeling of microwave circuits with bidirectional neural network models

Vai

et al. 1998

IEEE Trans. Microwave Theory Techn.

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Neural networks have been developed into an alternative modeling approach for the microwave circuit-design process. In this paper, we describe a neural network-based microwave circuit-design approach that implements the solution-searching optimization routine by a modified neural network learning process. Both the development of a microwave circuit model and the searching of a design solution can thus take advantage of a hardware neural network processor, which is significantly faster than a software simulation. In addition, a systematic simulation-based approach to convert conventional circuit models into neural network models for this design process will be described. The development of a heterojunction bipolar transistor (HBT) amplifier model and its applications are demonstrated.Index Terms-Neural network applications, modeling, optimization methods.

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“…Applications such as specialized numerical applications (e.g. encryption), DSP and image processing, cellular automata and other systolic arrays and neural networks have been demonstrated on a number of FPGA machines [3][4][5][6][7], each with many FPGAs connected to banks of memory, with speedups of 2 to 3 orders of magnitude over software quoted. However, the programming of even trivial tasks on these machines is complex and the development of support tools is an important ongoing research subject.…”

Section: Introductionmentioning

confidence: 99%

The Use of Field-Programmable Gate Arrays for the Hardware Acceleration of Design Automation Tasks

1996

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This paper investigates the possibility of using Field-Programmable Gate Arrays (Fr'GAS) as reconfigurable co-processors for workstations to produce moderate speedups for most tasks in the design process, resulting in a worthwhile overall design process speedup at low cost and allowing algorithm upgrades with no hardware modification. The use of FPGAS as hardware accelerators is reviewed and then achievable speedups are predicted for logic simulation and VLSI design rule checking tasks for various FPGA co-processor arrangements.

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GANGLION-a fast hardware implementation of a connectionist classifier

Cited by 20 publications

References 2 publications

VLSI Implementation of Deep Neural Network Using Integral Stochastic Computing

VLSI Implementation of Deep Neural Network Using Integral Stochastic Computing

Reverse modeling of microwave circuits with bidirectional neural network models

The Use of Field-Programmable Gate Arrays for the Hardware Acceleration of Design Automation Tasks

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