Neural networks have been developed into an alternative modeling approach for the microwave circuit-design process. In this paper, we describe a neural network-based microwave circuit-design approach that implements the solution-searching optimization routine by a modified neural network learning process. Both the development of a microwave circuit model and the searching of a design solution can thus take advantage of a hardware neural network processor, which is significantly faster than a software simulation. In addition, a systematic simulation-based approach to convert conventional circuit models into neural network models for this design process will be described. The development of a heterojunction bipolar transistor (HBT) amplifier model and its applications are demonstrated.Index Terms-Neural network applications, modeling, optimization methods.
ACHIEVING NEW LEVELS of integration and utilization in field-programmable logic requires new FPGA architectures. Problems with existing architectures include low resource utilization, routing congestion, high interconnect delay, and insufficient I/O connections. At Northeastern University, we have developed a novel three-dimensional FPGA architecture called Rothko, aimed at solving some of these problems. The technology underlying Rothko allows designers to stack two-dimensional CMOS circuits to build 3D VLSI structures. Vertical metal interconnects between layers (interlayer vias) can be placed anywhere on the chip. Overcoming problems One of the main obstacles to mapping large designs onto existing FPGA architectures is routing congestion. Although in current commercial FPGAs, routing resources take up a major part of the chip, implementing complex designs is often difficult due to a lack of routing resources. Routing resources in FPGAs are more expensive than in ASICs because FPGAs require programmable interconnect to maintain a flexible architecture. Programmable interconnect needs more area than fixed routing and introduces longer propagation delays. Segmented routing channels reduce the need for programmable interconnect, but buffers are necessary to drive signals, adding to circuit area. In addition, for signals that travel a long distance, delay can be significant. By going to a 3D design that allows flexible interconnect in every dimension, we expect to relieve routing congestion and shorten interconnect lengths dramatically, thus improving speed. An FPGA's speed is a measure of the delay required to implement a function and to propagate signals to neighboring functions. FPGA logic is often slow due to interconnect delay, which can account for over 70% of the clock cycle period. Another problem with FPGA designs is the number of I/O connections available. According to Rent's rule, the number of I/O pins needed on an FPGA grows faster than the square root of the number of logic elements. However, the number of perimeter bonding pads that can fit along the die periphery only grows as the square root of the area. This means that for a given pad pitch (about 100 microns) and logic element pitch, there is a die size beyond which the demand for I/O far exceeds the supply. In that case, the device becomes pin-limited. Experience with existing FPGAs shows that this results in low logic element utilization. Researchers have proposed using multichip modules (MCMs), area I/O, and optical interconnections to address some of these issues. 1-4 These technologies all require that
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