GangES: Gang error simulation for hardware resiliency evaluation

Abstract

As technology scales, the hardware reliability challenge affects a broad computing market, rendering traditional redundancy based solutions too expensive. Software anomaly based hardware error detection has emerged as a low cost reliability solution, but suffers from Silent Data Corruptions (SDCs). It is crucial to accurately evaluate SDC rates and identify SDC producing software locations to develop software-centric low-cost hardware resiliency solutions.A recent tool, called Relyzer, systematically analyzes an entire application's resiliency to single bit soft-errors using a small set of carefully selected error injection sites. Relyzer provides a practical resiliency evaluation mechanism but still requires significant evaluation time, most of which is spent on error simulations. This paper presents a new technique called GangES (Gang Error Simulator) that aims to reduce error simulation time. GangES observes that a set or gang of error simulations that result in the same intermediate execution state (after their error injections) will produce the same error outcome; therefore, only one simulation of the gang needs to be completed, resulting in significant overall savings in error simulation time. GangES leverages program structure to carefully select when to compare simulations and what state to compare. For our workloads, GangES saves 57% of the total error simulation time with an overhead of just 1.6%. This paper also explores pure program analyses based techniques that could obviate the need for tools such as GangES altogether. The availability of Relyzer+GangES allows us to perform a detailed evaluation of such techniques. We evaluate the accuracy of several previously proposed program metrics. We find that the metrics we considered and their various linear combinations are unable to adequately predict an instruction's vulnerability to SDCs, further motivating the use of Relyzer+GangES style techniques as valuable solutions for the hardware error resiliency evaluation problem.

Finding Resilience-Friendly Compiler Optimizations Using Meta-Heuristic Search Techniques

“…Figure 4.4B plots the estimated SDC rate by the regression model against the actual SDC rate for 5 benchmark programs with 10 different compiler optimizations. As can be seen from the figure, the estimated SDC rate by the model has very poor correlation with the actual SDC rate (a similar result was obtained by Hari et al [12]). Therefore, it is nontrivial to determine the error resilience of the program using these factors, and hence we use a fault injection experiment for fitness function and score calculation in our approaches.…”

Versatile architecture-level fault injection framework for reliability evaluation: A first report

“…In [30] a fault injection tool based on the cycle accurate full system simulator Gem5 is proposed. Authors of [14] propose a technique to reduce the fault simulation time through grouping error simulations that produce same intermediate execution state. In [25], a statistical method to estimate the outcome of a system in presence of soft errors is proposed.…”

Evaluation of Histogram of Oriented Gradients Soft Errors Criticality for Automotive Applications

“…The intrinsic limitations of fault-injection on COTS make it impossible to correlate each physical radiation-induced error with its manifestation at the output. However, by corrupting variable values, we are able to identify those parts of the code that are likely to affect HOG execution [Hari et al 2014]. In other words, we can calculate the SDC rate for HOG, which is the percentage of injected errors that caused SDCs.…”