GaAs MQW modulators integrated with silicon CMOS

Goossen, K.W.; Walker, James Alfred; D'Asaro, L.A.; Hui, S.P.; Tseng, B.; Leibenguth, R.E.; Kossives, D.; Bacon, D. D.; Dahringer, D.; Chirovsky, L. M. F.; Lentine, Anthony L.; Miller, D. A. B.

doi:10.1109/68.376802

Cited by 233 publications

(62 citation statements)

References 10 publications

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“…In this system, optical connections are made directly from the surface of the silicon chip to the other switching machines, avoiding entirely the usual hierarchy of repeatered electrical interconnections. Such radical approaches are possible because of emerging technology that allows large numbers of high-speed optical interconnections directly in and out of silicon chips [7].…”

Section: Introductionmentioning

confidence: 99%

Limit to the Bit-Rate Capacity of Electrical Interconnects from the Aspect Ratio of the System Architecture

Miller

Özaktaş

1997

Journal of Parallel and Distributed Computing

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234

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We show that there is a limit to the total number of bits per second, B, of information that can flow in a simple digital electrical interconnection that is set only by the ratio of the length " of the interconnection to the total cross-sectional dimension A of the interconnect wiring -the "aspect ratio" of the interconnection. This limit is largely independent of the details of the design of the electrical lines. The limit is approximately B ~ B o A/" 2 bits/s, with B o ~ 10 15 (bit/s) for highperformance strip lines and cables, ~10 16 for small on-chip lines, and ~10 17 -10 18 for equalized lines. Because the limit is scale-invariant, neither growing or shrinking the size of the system substantially changes the limit. Exceeding this limit requires techniques such as repeatering, coding, and multilevel modulation. Such a limit will become a problem as machines approach Tb/s information bandwidths. The limit will particularly affect architectures in which one processor must talk reasonably directly with many others. We argue that optical interconnects can solve this problem since they avoid the resistive loss physics that gives this limit.

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Section: Introductionmentioning

confidence: 99%

Limit to the Bit-Rate Capacity of Electrical Interconnects from the Aspect Ratio of the System Architecture

Miller

Özaktaş

1997

Journal of Parallel and Distributed Computing

Self Cite

234

136

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“…Although some optoelectronic integration techniques, such as solderbump bonding, 16 allow optoelectronics to be placed directly above silicon circuitry, thereby slightly altering trace-line routing conditions, the assumption made here was that the cluster would be too densely packed to allow logic to be placed between windows and that trace lines would be the only features present within the cluster.…”

Section: Interconnection Modelmentioning

confidence: 99%

“…Although, in principle, transistors may be placed within and below the cluster, depending on the type of technology used, 16 it was assumed that this would be a region where trace lines would be most densely packed and hence void of transistors. It follows that the number of transistors is given by…”

Section: Interconnection Modelmentioning

confidence: 99%

Reconfigurable intelligent optical backplane for parallel computing and communications

Szymański

Hinton

1996

Appl. Opt.

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A design analysis of a telecentric microchannel relay system developed for use with a smart-pixel-based photonic backplane is presented. The interconnect uses a clustered-window geometry in which optoelectronic device windows are grouped together about the axis of each microchannel. A Gaussianbeam propagation model is used to analyze the trade-off between window size, window density, transistor count per smart pixel, and lenslet f-number for three cases of window clustering. The results of this analysis show that, with this approach, a window density of 4000 windows@cm 2 is obtained for a window size of 30 µm and a device plane separation of 25 mm. In addition, an optical power model is developed to determine the nominal power requirements of a 32 3 32 smart-pixel array as a function of window size. The power requirements are obtained assuming a complementary metal-oxide semiconductor inverter-amplifier and dual-rail multiple-quantum-well self-electro-optic-effect devices as the receiver stage of the smart pixel. r

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“…With this term we refer to planar electronic circuits with optical input-output capability from their surface. ͑The term smart pixels 73 is also used to describe such device planes, but we find that term to have restrictive connotations and thus avoid using it.͒ For instance, flip-chip bonding of self-electrooptic-effect devices ͑SEED's͒ on silicon 74,75 or other smart-pixel technologies 76 -84 would allow the construction of such device planes. A device plane may actually consist of several active device layers sandwiched together so as to constitute an effective single device plane.…”

Section: ͞2mentioning

confidence: 99%

Toward an optimal foundation architecture for optoelectronic computing Part I Regularly interconnected device planes

Özaktaş

1997

Appl. Opt.

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By systematically examining the tree of possibilities for optoelectronic computing architectures and offering arguments that allow one to prune suboptimal branches of this tree, I come to the conclusion that electronic circuit planes interconnected optically according to regular connection patterns represent an alternative that is reasonably close to the best possible, as defined by physical limitations. Thus I propose that this foundation architecture should provide a basis for future research and development in this area.

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GaAs MQW modulators integrated with silicon CMOS

Cited by 233 publications

References 10 publications

Limit to the Bit-Rate Capacity of Electrical Interconnects from the Aspect Ratio of the System Architecture

Limit to the Bit-Rate Capacity of Electrical Interconnects from the Aspect Ratio of the System Architecture

Reconfigurable intelligent optical backplane for parallel computing and communications

Toward an optimal foundation architecture for optoelectronic computing Part I Regularly interconnected device planes

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