GaAs MOSFETs fabrication with a selective liquid phase oxidized gate

Wu, Jin-Shang; Wang, Hwei-Heng; Wang, Yeong-Her; Houng, Mau–Phon

doi:10.1109/16.915668

Cited by 13 publications

(1 citation statement)

References 18 publications

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“…In this section, device characteristics of D-mode GaAs MOS-FET's from various research groups are summarized in Table V. [9][10][11][12][13][40][41][42][43][44][45][46][47][48] The drain current drift and hysteresis in the past hindered the deployment of GaAs MOSFET's due to inadequate insulating films with significant bulk trapped charges and a high D it on GaAs has now been decreased or eliminated. Theoretical studies predicate that MOSFET should have about 20 -40% higher unity current gain off frequency ( f t ) than MESFET.…”

Section: Depletion-mode Mosfet's and Power Eevicesmentioning

confidence: 99%

III–V Metal–Oxide–Semiconductor Field-Effect Transistors with High κ Dielectrics

Hong

Kwo

Tsai

et al. 2007

jjap

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Research efforts on achieving low interfacial density of states (Dit) as well as low electrical leakage currents on GaAs-based III–V compound semiconductors are reviewed. Emphasis is placed on ultra high vacuum (UHV) deposited Ga2O3(Gd2O3) and atomic layer deposition (ALD)-Al2O3 on GaAs and InGaAs. Ga2O3(Gd2O3), the novel oxide, which was electron-beam evaporated from a gallium-gadolinium-garnet target, has, for the first time, unpinned the Fermi level of the oxide/GaAs heterostructures. Interfacial chemical properties and band parameters of valence band offsets and conduction band offsets in the oxides/III–V heterostructures are studied and determined using X-ray photoelectron spectroscopy and electrical leakage transport measurements. The mechanism of III–V surface passivation is discussed. The mechanism of Fermi-level unpinning in ALD-Al2O3ex-situ deposited on InGaAs were studied and unveiled. Systematic heat treatments under various gases and temperatures were studied to achieve low leakage currents of 10-8–10-9 A/cm2 and low Dit's in the range of (4–9)×1010 cm-2 eV-1 for Ga2O3(Gd2O3) on InGaAs. By removing moisture from the oxide, thermodynamic stability of the Ga2O3(Gd2O3)/GaAs heterostructures was achieved with high temperature annealing, which is needed for fabricating inversion-channel metal–oxide–semiconductor filed-effect transistors (MOSFET's). The oxide remains amorphous and the interface remains intact with atomic smoothness and sharpness. Device performances of inversion-channel and depletion-mode III–V MOSFET's are reviewed, again with emphasis on the devices using Ga2O3(Gd2O3) as the gate dielectric.

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Section: Depletion-mode Mosfet's and Power Eevicesmentioning

confidence: 99%

III–V Metal–Oxide–Semiconductor Field-Effect Transistors with High κ Dielectrics

Hong

Kwo

Tsai

et al. 2007

jjap

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n‐Channel p‐channel enhancement/inversion mode GaAs‐MISFETs with gate insulating layers formed by dry oxi‐nitridation

Tametou

Takebe

Paul

et al. 2006

Electron Comm Jpn Pt II

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SUMMARYTest fabrication of n-channel p-channel enhancement/inversion mode GaAs-MISFET with a GaAs oxy-nitrided gate insulation film formed by nitriding after oxidation of the GaAs surface was performed. In comparison with MOSFET with only oxidation, the pinch-off and hysteresis characteristics are improved in MISFET. The confirmed values of the transconductance are 62 mS/mm (V th ~ 0 V), 41 mS/mm (V th ~ 1 V), and 14 mS/mm [V th = V flat (= 1.1 V)] for the n-channel type. These values are 10 to 100 times those reported previously in GaAs-MOSFET. The result realized for the p-channel type MISFET is about 9 mS/mm.

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Channel Material Engineered Nanoscale Cylindrical Surrounding Gate MOSFET with Interface Fixed Charges

Gautam

Saxena

Gupta

et al. 2011

Trends in Network and Communications

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GaAs MOSFETs fabrication with a selective liquid phase oxidized gate

Cited by 13 publications

References 18 publications

III–V Metal–Oxide–Semiconductor Field-Effect Transistors with High κ Dielectrics

III–V Metal–Oxide–Semiconductor Field-Effect Transistors with High κ Dielectrics

n‐Channel p‐channel enhancement/inversion mode GaAs‐MISFETs with gate insulating layers formed by dry oxi‐nitridation

Channel Material Engineered Nanoscale Cylindrical Surrounding Gate MOSFET with Interface Fixed Charges

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