GaAs MOSFET with oxide gate dielectric grown by atomic layer deposition

Ye, P.D.; Wilk, G. D.; Kwo, J.; Yang, Bong-Jun; Gossmann, H.‐J.; Frei, M.; Chu, S. N. G.; Mannáerts, J. P.; Sergent, M.; Hong, M.; Ng, Kwok K.; Bude, J.

doi:10.1109/led.2003.812144

Cited by 235 publications

(115 citation statements)

References 20 publications

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“…This was a real breakthrough since by then, this was thought not to be possible. More significantly, in 2003, Al 2 O 3 deposited by ALD an ex-situ technique, also yielded an excellent interface on GaAs [3]. This was soon observed with other oxides and III-V semiconductors.…”

Section: Towards Thz Ingaas Fetsmentioning

confidence: 86%

“…Separately and following the first demonstration of GaAs MOSFETs using an ALD oxide [3], InGaAs MOSFETs were also demonstrated with increasing InAs composition in the channel [29,30,31]. As with HEMTs, the performance of these devices was seen to improve as more InAs was introduced in the channel [32].…”

Section: Towards Ingaas Mosfets For Cmosmentioning

confidence: 99%

“…However, in the last few years, there have been many demonstrations of Fermilevel unpinned oxide/III-V interfaces that strongly suggest that this is an eminently engineerable problem. Of even greater significance is the fact that some of these techniques are manufacturable, such as Atomic Layer Deposition (ALD) [3]. This has spurred a veritable race to demonstrate nano-scale InGaAs MOSFETs suitable for sub-10 nm CMOS.…”

Section: Introductionmentioning

confidence: 99%

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Nanometer-scale InGaAs field-effect transistors for THz and CMOS technologies

Alamo

2013

2013 Proceedings of the European Solid-State Device Research Conference (ESSDERC)

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Abstract-Integrated circuits based on InGaAs Field EffectTransistors are currently in wide use in the RF front-ends of smart phones and other mobile platforms, wireless LANs, high data rate fiber-optic links and many defense and space communication systems. InGaAs ICs are also under intense research for new millimeter-wave applications such as collision avoidance radar and gigabit WLANs. InGaAs FET scaling has nearly reached the end of the road and further progress to propel this technology to the THz regime will require significant device innovations. Separately, as Si CMOS faces mounting difficulties to maintain its historical density scaling path, InGaAs-channel MOSFETs have recently emerged as a credible alternative for mainstream logic technology capable of scaling to the 10 nm node and below. To get to this point, fundamental technical problems had to be solved though there are still many challenges to be addressed before the first non-Si CMOS technology becomes a reality. The intense research that this exciting prospect is generating is also reinvigorating the prospects of InGaAs FETs to become the first true THz electronics technology. This paper reviews progress and challenges of InGaAs-based FET technology for THz and CMOS.

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Section: Towards Thz Ingaas Fetsmentioning

confidence: 86%

Section: Towards Ingaas Mosfets For Cmosmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

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Nanometer-scale InGaAs field-effect transistors for THz and CMOS technologies

Alamo

2013

2013 Proceedings of the European Solid-State Device Research Conference (ESSDERC)

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“…The main obstacle is the lack of high-quality, thermodynamically stable dielectric on GaAs that can match the device criteria as SiO 2 on Si such as a mid-gap interface trap density (D it ) around 10 10 cm -2 eV -1 . During the past decades, tremendous efforts have been made to improve the oxide/GaAs interface with most of focus on different types of oxides and formation methods [2][3][4][5][6][7][8][9][10] . Recent work finds that the oxide/GaAs interface quality is strongly dependent on semiconductor surface orientations.…”

mentioning

confidence: 99%

Inversion-mode GaAs wave-shaped field-effect transistor on GaAs (100) substrate

Zhang

Lou

et al. 2015

Applied Physics Letters

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Inversion-mode GaAs wave-shaped metal-oxide-semiconductor field-effect transistors (WaveFETs) are demonstrated using atomic-layer epitaxy of La2O3 as gate dielectric on (111)A nano-facets formed on a GaAs (100) substrate. The wave-shaped nano-facets, which are desirable for the device on-state and off-state performance, are realized by lithographic patterning and anisotropic wet etching with optimized geometry. A well-behaved 1 μm gate length GaAs WaveFET shows a maximum drain current of 64 mA/mm, a subthreshold swing of 135 mV/dec, and an ION/IOFF ratio of greater than 107.

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“…MOSFETs. This work and [12,[14][15][16][17] were carried out on GaAs wafers, but [13] used an InP substrate, allowing the use of a higher indium concentration channel with higher mobility, which should translate into higher drive current and higher transconductance. Despite this, the data presented in this letter represents an increase in g m of 68% over the previously published best results [12].…”

mentioning

confidence: 99%