Future of Nanoscale Strained Si/SixGe1–x Metal-Oxide Semiconductor Field-Effect Transistor for Performance Metric Evaluation: A Review

Kang, EngSiew; Hamid, F. K. A.; Ismail, Razali

doi:10.1166/jno.2014.1608

Cited by 5 publications

(3 citation statements)

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“…Because of Type-II band heterogeneity in s-Si and s-SiGe layer, conduction band breaks into two fold and four fold valleys evolving in decrement of effective mass [23,24]. Therefore, the effective mobility charge carrier is improved which is given by the relation [25] e m 1 ( )…”

Section: Device Structure and Theorymentioning

confidence: 99%

Exploration of effects of gate underlap in HOI FinFETs at 10 nm gate length

Datta,

Nanda,

Sankar Dhar

2023

Phys. Scr.

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With sub-22 nm technology nodes, the short channel effects (SCEs) arose in FinFETs, which hindered the further scaling of devices. The leakage currents became detrimental with scaling of the gate oxide thickness below 2 nm, hence the demand for control of leakage currents due to corner effects in the sidewalls of FinFETs. Research suggested use of gate underlap (GUL) architectures to suppress the leakage currents. The objective of this paper is to utilize a GUL structure in a 10 nm gate length Heterostructure-On-Insulator (HOI) FinFET, encompassing a three layered strained channel architecture to enrich the drive currents. Different structures with GUL lengths of 1 nm, 3 nm and 5 nm are designed to study the electrical characteristics besides the effects of leakage currents and other SCEs. A noteworthy decrease is observed in the leakage currents with increasing GUL lengths. However, it also leads to decrease of drive currents of the devices. A trade-off between the enhanced dimensions of source/drain along with an optimized GUL length proves beneficial in the strained silicon channel devices. The 10 nm HOI device employing a 3 nm GUL with height/width of source/drain at 8 nm provides drive currents and leakage currents at par with the 10 nm HOI device with no underlap. But with higher Ion/Ioff current ratio and lower SCEs, this device with 3 nm underlap decreases corner effects and is observed from the electron velocity and total current density contours leading to faster switching speeds and optimized device performance towards semiconductor industry.

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Section: Device Structure and Theorymentioning

confidence: 99%

Exploration of effects of gate underlap in HOI FinFETs at 10 nm gate length

Datta,

Nanda,

Sankar Dhar

2023

Phys. Scr.

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“…The channel region of DG NanoFET comprises of three layers forming the hetero-layered architecture (s-Si/ s-SiGe/s-SiGe). Due to Type-II band heterogeneity in s-Si and s-SiGe layer, conduction band splits into two fold and four fold valleys resulting in decrease of effective mass [17,18] hence the effective charge carrier mobility increases and is given by the relation [19]…”

Section: Theory and Device Structurementioning

confidence: 99%

“…whered s Si and d SiGe are different lattice thicknesses in channel region as shown in figure 1(b), and d soi is the buried oxide thickness. The carrier transport, stress quantization effect and effective carrier density in different valleys are analysed with the multivalley band structure model including Modified Local Density Approximation (MLDA) in the device simulation [18][19][20]. The Poisson's and Carrier Continuity equations are applied concurrently within the strain channel and dielectric interfaces specifying the boundary condition, while instantaneously applying non local mesh for carrier confinement in the two s-Si layers for nano channel length devices.…”

Section: Theory and Device Structurementioning

confidence: 99%

Exploration of improved leakage based performance analysis for underlap induced strained-Si layer in tri-layered channel DG nanoFETs

Kumar¹,

Dhar²

2021

Phys. Scr.

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Induction of gate underlap with strained tri-layered (s-Si/s-SiGe/s-Si) HOI channel system in Double Gate NanoFET at 14 nm technology node is developed to provide a promising substitute expecting to overcome the glitches of short channel effects at nano regime. In the newly designed devices, the gate underlap length is varied from 1 nm to 8 nm for three segments of devices (i) full channel (ii) s-Si layer of channel and (iii) s-SiGe layer of channel. The newly developed devices are then compared with existing DG FET. The leakage current is observed to reduce exponentially with increase in underlap length for the first two options, which directly attributes to curtail gate tunneling and thereby a novel Decay Current equation restraining to underlap is proposed. The DG NanoFET with strained silicon layer of channel for 1 nm gate underlap length (Device B) showed improvement by 25.3% decrement in DIBL and 88.8% increment in V th . The strain in silicon layer enhances carrier mobility and instates ballistic transport through the quantum well of the channel system resulting in 33% enriched drive current and is proposed as the most suitable and improved device in nano regime.

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Asymmetric, compressive, SiGe epilayers on Si grown by lateral liquid-phase epitaxy utilizing a distinction between dislocation nucleation and glide critical thicknesses

O’Reilly

Quitoriano

2018

Journal of Crystal Growth

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Future of Nanoscale Strained Si/Si_xGe_1–x Metal-Oxide Semiconductor Field-Effect Transistor for Performance Metric Evaluation: A Review

Cited by 5 publications

References 0 publications

Exploration of effects of gate underlap in HOI FinFETs at 10 nm gate length

Exploration of effects of gate underlap in HOI FinFETs at 10 nm gate length

Exploration of improved leakage based performance analysis for underlap induced strained-Si layer in tri-layered channel DG nanoFETs

Asymmetric, compressive, SiGe epilayers on Si grown by lateral liquid-phase epitaxy utilizing a distinction between dislocation nucleation and glide critical thicknesses

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