Future execution: a hardware prefetching technique for chip multiprocessors

Abstract

This paper proposes a new hardware technique for using one core of a CMP to prefetch data for a thread running on another core. Our approach simply executes a copy of all non-control instructions in the prefetching core after they have executed in the primary core. On the way to the second core, each instruction's output is replaced by a prediction of the likely output that the n th future instance of this instruction will produce. Speculatively executing the resulting instruction stream on the second core issues load requests that the main program will probably reference in the future. Unlike previously proposed thread-based prefetching approaches, our technique does not need any thread spawning points, features an adjustable lookahead distance, does not require complicated analyzers to extract prefetching threads, is recovery-free, and necessitates no storage for the prefetching threads. We demonstrate that for the SPECcpu2000 benchmark suite, our mechanism significantly increases the prefetching coverage and improves the primary core's performance by 10% on average over a baseline that already includes an aggressive hardware stream prefetcher. We further show that our approach works well in combination with runahead execution.

Data access history cache and associated data prefetching mechanisms

“…Some polynomial formula is used to predict the future access for general cases. For example, if a constant difference is found in the third depth, the future access is predicted as Figure 3 shows an example where a complex structure pattern (4,8,4,8) is detected when we perform the MLDT prefetching with the DAHC.…”

“…Other recent efforts in hardware prefetching include Zhou's dual-core execution (DCE) approach [23] , Ganusov et al's future execution (FE) approach [8] , Sun et al's data push server architecture [21] and Solihin et al's memory-side prefetching [20] .…”

A Speculative Technique for Auto-Memoization Processor with Multithreading

“…Next, input matching starts. This process is shown as (1)... (8) in Fig.4. First, the memoization engine reads the value of program counter (PC) and registers.…”

“…This extension can omit the execution of instruction regions whose inputs show monotonous increase/decrease. These SpMT cores not only omit some execution, but also works as a cache prefetch technique [7], [8].…”

Taxonomy of Data Prefetching for Multicore Processors

“…Many of these methods run a helper thread ahead of actual execution of an application to predict cache misses [10−15] . Another set of methods employ run-ahead execution at hardware level [16,17] , where idle or dedicated cycles are used for prefetching. We proposed to utilize a dedicated server to push data closer to CPU by selecting future data access prediction methods dynamically [18] .…”