Fundamentals of Next Generation Compact MOSFET Models

“…There has been a great deal of discussion [1][2][3][4] about the convenience of using either surface potential-based or charge-based formulations for developing MOSFET compact models. On the other hand, it is convenient that the models be formulated in such a generalized manner that they remain valid for various device configurations and operating conditions.…”

Section: Introductionmentioning

confidence: 99%

Unification of asymmetric DG, symmetric DG and bulk undoped-body MOSFET drain current

Ortíz‐Conde

Sánchez

2006

Solid-State Electronics

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“…This analytical approach provides better accuracy and independently lacks the device and model parameters. A physics-based analytical model [5][6][7] is a surface-inversion charge potential approach. The defined model linearizes surface-inversion charge density factors to improve accuracy with high complex equations and parameters.…”

mentioning

confidence: 99%

A Unified Power-Delay Model for GDI Library Cell Created Using New Mux Based Signal Connectivity Algorithm

Ponnian¹,

Pari²,

Ramadass³

et al. 2023

Emerg Sci J

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The challenges of innovative IC technology typically come with various new design constraints in terms of circuit implementation, behaviour, scaling, and an accurate power-delay model to evaluate the circuit's performance. The circuit realization technique using GDI is gaining popularity because of its power and transistor utilization factors. Considering the core advantage of the GDI technique, this research presents the creation of new GDI library cells implemented using the MUX-based algorithm and its delay-power model. This research defines two goals; the former goal depicts the proposal of GDI library cells with full swing using a MUX-based signal connectivity model, and the later presents the mathematical delay-power model for the proposed GDI library cells. The number of attributes defined in the delay and power model incorporates minimum variables without sacrificing precision. It calculates the delay for simple RC networks and combinational circuits with multiple paths. The power model is given using the node activity factor and the power factor related to the internal node capacitances, wiring, and gate capacitances of the driving and receiving GDI nodes. The experimental results of this study, which conform to the specifications of the sub-micron library supported for the SilTerra 130 nm 6-metal layer fabricated for the CMOS n-well process, demonstrate that the proposed GDI library is indeed superior in terms of delay-transistor and power utilisation to PTL and CMOS technology. The simulation results reveal that there is 55 to 65 % improvement in terms of power and delay factor with the existing CMOS and PTL logic. The proposed delay model demonstrates that GDI cells require less logical effort than CMOS technology. The proposed power model shows that the node activity factor of the proposed GDI cells lies between 0.1 and 0.2, while in CMOS, it is between 0.1 and 0.3. Doi: 10.28991/ESJ-2023-07-04-022 Full Text: PDF

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Fundamentals of Next Generation Compact MOSFET Models

Cited by 3 publications

References 14 publications

Fundamentals, Computer Implementation and Applications of the Advanced Compact MOSFET (ACM) Model

Fundamentals, Computer Implementation and Applications of the Advanced Compact MOSFET (ACM) Model

Unification of asymmetric DG, symmetric DG and bulk undoped-body MOSFET drain current

A Unified Power-Delay Model for GDI Library Cell Created Using New Mux Based Signal Connectivity Algorithm

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