Fundamental efficiency limits in power electronic systems

Heckel, Thomas; Rettner, Cornelius; März, Martin

doi:10.1109/intlec.2015.7572399

Cited by 13 publications

(6 citation statements)

References 7 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…This D-FOM does not require knowledge of the die area of the device, as R ′ on C ′ oss,Q = R on C oss,Q , and the D-FOM for a given semiconductor therefore can be determined from nonproprietary datasheet parameters. Similar device FOMs that depend on R ′ on and the differential C ′ oss [6] and energyequivalent output capacitance C ′ oss,E [10,36,37] have been reported, but the C oss,Q dependency proposed here is the correct metric to determine the minimum hard-switching losses of a half-bridge. Finally, we can rewrite (8) compactly as:…”

Section: Optimal Power Semiconductor Losses For Two-level Bridgementioning

confidence: 55%

See 1 more Smart Citation

New Figure-of-Merit Combining Semiconductor and Multi-Level Converter Properties

Anderson

Zulauf

Kolar

et al. 2020

IEEE Open J. Power Electron.

View full text Add to dashboard Cite

Figures-of-merit (FOMs) are widely-used to compare power semiconductor materials and devices and to motivate research and development of new technology nodes. These material-and device-specific FOMs, however, fail to directly translate into quantifiable performance in a specific power electronics application. Here, we combine device performance with specific bridge-leg topologies to propose the extended FOM, or X-FOM, a figure-of-merit that quantifies bridge-leg performance in multi-level (ML) topologies and supports the quantitative comparison and optimization of topologies and power devices. To arrive at the proposed X-FOM, we revisit the fundamental scaling laws of the on-state resistance and output capacitance of power semiconductors to first propose a revised device-level semiconductor Figure-of-Merit (D-FOM). The D-FOM is then generalized to a multi-level topology with an arbitrary number of levels, output power, and input voltage, resulting in the X-FOM that quantitatively compares hard-switched semiconductor stage losses and filter stage requirements across different bridgeleg structures and numbers of levels, identifies the maximum achievable efficiency of the semiconductor stage, and determines the loss-optimal combination of semiconductor die area and switching frequency. To validate the new X-FOM and showcase its utility, we perform a case study on candidate bridge-leg structures for a three-phase 10 kW photovoltaic (PV) inverter, with the X-FOM showing that (a) the minimum hard-switching losses are an accurate approximation to predict the theoretically maximum achievable efficiency and relative performance between bridge-legs and (b) the 3-level bridge-leg outperforms the 2-level configuration, despite utilizing a SiC MOSFET with a lower D-FOM than in the 2-level case.

show abstract

Section: Optimal Power Semiconductor Losses For Two-level Bridgementioning

confidence: 55%

“…However, since the capacitance as a function of voltage u (and not x) is desired, by integrating the voltage u over x (see (36)) and solving for x with use of (31):…”

Section: B Switching Losses: C ′mentioning

confidence: 99%

New Figure-of-Merit Combining Semiconductor and Multi-Level Converter Properties

Anderson

Zulauf

Kolar

et al. 2020

IEEE Open J. Power Electron.

View full text Add to dashboard Cite

show abstract

“…• Device figure-of-merit (DFOM) [94]; this FOM includes the correct capacitive loss contribution in hard-switching bridgelegs, leveraging the charge-equivalent output capacitance C oss,Q defined in [74], as opposed to the energy-equivalent one used in [91]- [93]:…”

Section: B Review Of Existing Fomsmentioning

confidence: 99%

New FOM-Based Performance Evaluation of 600/650 V SiC and GaN Semiconductors for Next-Generation EV Drives

2022

View full text Add to dashboard Cite

in 1993, and the Ph.D. in Electrical Engineering from Politecnico di Torino, Italy, in 2002. He is a Full Professor of Power Electronics and Electrical Drives in the Energy Department "G. Ferraris" and Chairman of the Power Electronics Innovation Center (PEIC) at Politecnico di Torino, Italy. Dr. Bojoi published more than 200 papers covering electrical drives and power electronics for industrial applications, transportation electrification, power quality, and home appliances. He was involved in many research projects with industry for direct technology transfer aiming at obtaining new products. Dr. Bojoi is the co-recipient of 6 IEEE prize paper awards. Dr. Bojoi is a Co-Editor-In-Chief of the IEEE Transactions on Industrial Electronics.

show abstract

“…According to the contours in Figure 3b, there is an optimum chip size for each switching frequency, which does not necessarily result in the lowest on-state resistance. The authors in [40] found that this optimum is located at the intersection of the dynamic losses P dyn and static losses P stat for the respective chip size, and depends on the transistor current and the switching frequency. With increasing switching frequency, the optimum chip size decreases, i.e., the on-state resistance R DSon rises and the output capacitance decreases.…”

Section: Evaluation Of Pfc Topologymentioning

confidence: 99%

A High-Efficiency High-Power-Density SiC-Based Portable Charger for Electric Vehicles

et al. 2022

View full text Add to dashboard Cite

This paper proposes a portable 11 kW off-board charger for electric vehicles. In the ac/dc stage, a three-phase power factor correction (PFC) in Vienna topology is chosen. The loss and volume of the PFC inductance are calculated over a wide range of parameters and optimized with regard to design, winding, and core material. A three-phase LLC resonant converter operating at 1 MHz is chosen for the galvanically isolated dc/dc stage. A parametrizable loss model of the high-frequency transformer and the resonance inductor is developed to minimize volume, weight, and losses. With the help of an automated algorithm using these loss models, the inductive components are optimized in terms of winding specification, magnetic material, and core geometry, verified by finite element analysis and measurements. For the ac/dc stage, 900 V SiC devices are adopted, and 1200 V SiC devices are used in the primary and secondary sides of the dc/dc stage. A variable dc-link voltage is utilized to adjust the charging profile and to operate the LLC resonant converter at the most efficient point near the series resonance frequency. A mechatronically integrated portable air-cooled off-board charger prototype with 11 kW, three-phase 400 VAC input, and 620–850 VDC output is realized and tested. The prototype demonstrates a power density of 2.3 kW/liter (37.7 W/in³), a peak efficiency of 96%, and 95.8% efficiency over the defined battery voltage range.

show abstract

Fundamental efficiency limits in power electronic systems

Cited by 13 publications

References 7 publications

New Figure-of-Merit Combining Semiconductor and Multi-Level Converter Properties

New Figure-of-Merit Combining Semiconductor and Multi-Level Converter Properties

New FOM-Based Performance Evaluation of 600/650 V SiC and GaN Semiconductors for Next-Generation EV Drives

A High-Efficiency High-Power-Density SiC-Based Portable Charger for Electric Vehicles

Contact Info

Product

Resources

About