Functional Verification of Power Gated Designs by Compositional Reasoning

Abstract

Power gating is a technique for low power design in which whole sections of the chip are powered off when they are not needed, and powered back on when they are. Functional correctness of power gating is usually checked as part of system-level verification, where the most widely used technique is simulation using pseudo-random stimuli. We propose instead to perform a sequential equivalence check between the power gated design and a version of itself in which power gating is disabled. We take a compositional approach that looks for partial equivalence of each unit under a suitable set of assumptions, guaranteed by the neighboring units. We make use of so-called circular reasoning rules to compose the partial equivalences proved on the individual units back into total equivalence on the whole chip.

Formal Verification of System-Level Power Management Architecture in Modern Processors

“…1 Power management strategy 2 System level 3 Low-power intent 4 Unified Power Format (UPF) 5 Register-transfer level (RTL) 6 Gate level 7 Transaction level (TL) 8 Electronic system level (ESL) 9…”

Minimizing Expected Cost Under Hard Boolean Constraints, with Applications to Quantitative Synthesis

“…As the chips become more complex, the cost of powering a server farm can easily outweigh the cost of the servers themselves, thus design teams go to great lengths in order to reduce power consumption in their designs. The most widely researched logical power saving techniques are clock gating, in which a clock is prevented from making a "tick" if it is redundant (c.f., [4]), and power gating, in which whole sections of the chip are powered off when not needed and then powered on again [15,14]. The goal of these techniques is to reduce power consumption and the number of changes in the values of signals, the main source of power consumption in chips.…”

Open SystemC Simulator with Support for Power Gating Design

“…Functional verification is a processes used in order to demonstrate that the objectives of the design are preserved after its implementation [5]. In accordance with the state of the art, the power gating verification process has been executed at the Register-Transfer Level (RTL) [6][7][8][9], primarily, based on Common Power Format (CPF) and Unified Power Format (UPF) [10][11][12][13][14][15]. The purpose of this work is to demonstrate a SystemC simulator, open source, with support to functional verification of designs containing the principles of the power gating technique implemented in SystemC RTL.…”