Functional unit sharing between stacked processors in 3D integrated systems

Borodin, Demid; Siauw, Winston; Cotofana, Sorin

doi:10.1109/samos.2011.6045477

Cited by 4 publications

(2 citation statements)

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“…Still, each engine requires a queue and other data to keep track of producers and consumers which result in a complex design. In [Borodin et al 2011], authors propose the sharing of functional units across cores in a 3D stacked die for online testing and/or performance improvement. A similar approach to 3D resource sharing was proposed in [Homayoun et al 2012] where the Reorder Buffer (ROB), register file, instruction queue and the load/store queues were shared.…”

Section: Related Workmentioning

confidence: 99%

Does the Sharing of Execution Units Improve Performance/Power of Multicores?

Rodrigues

Koren

Kundu

2015

ACM Trans. Embed. Comput. Syst.

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Several studies and recent real world designs have promoted sharing of underutilized resources between cores in a multicore processor to achieve better performance/power. It has been argued that when utilization of such resources is low, sharing has negligible impact on performance, while offering considerable area and power benefits . In this paper we investigate the performance and performance/Watt implications of sharing large and underutilized resources between pairs of cores in a multicore. We first study sharing of the entire floating-point datapath (including reservation stations and execution units) by two cores, similar to AMD's Bulldozer. We find that while this architecture results in power savings, for certain workload combinations, it also results in significant performance loss of about 28%. Next, we study an alternative sharing architecture where only the floating-point execution units are shared, while the individual cores retain their reservation stations. This reduces the performance loss to 14%. We then extend the study to include sharing of other large execution units that are used infrequently, namely the integer multiply and divide units. Subsequently, we analyze the impact of sharing hardware resources in Simultaneously MultiThreaded (SMT) processors where multiple threads run concurrently on the same core. It is observed that sharing improves performance/Watt at a negligible performance cost only if the shared units have high throughput. Sharing low throughput units reduces both performance and performance/Watt. To increase the throughput of the shared units we propose the use of Dynamic Voltage and Frequency Boosting (DVFB) of only the shared units that can be placed on a separate voltage island. Our results indicate that the use of DVFB improves both performance and performance/Watt by as much as 22% and 10%, respectively.

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Section: Related Workmentioning

confidence: 99%

Does the Sharing of Execution Units Improve Performance/Power of Multicores?

Rodrigues

Koren

Kundu

2015

ACM Trans. Embed. Comput. Syst.

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“…In [20] the vertical proximity of hardware is exploited and functional unit sharing is proposed that makes use of fast vertical access between these resources in order to improve the system reliability and/or performance.…”

Section: Introductionmentioning

confidence: 99%

Zero-performance-overhead online fault detection and diagnosis in 3D stacked integrated circuits

Safiruddin

Lefter

Borodin

et al. 2012

Proceedings of the 2012 IEEE/ACM International Symposium on Nanoscale Architectures

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In this paper we present a zero-performanceoverhead online fault detection and diagnosis scheme that exploits the vertical proximity of hardware inherent in 3D stacked integrated circuits (3D-SIC). We consider a 3D stacked processor executing independent instruction streams from different threads, on each die. We propose the vertical clustering of functionally identical computational blocks in order to enable the utilization of the 3D specific low-latency interlayer communication infrastructure. The clustering facilitates the parallel re-execution of instructions on idle units located in the proximity of the units which initially computed them and in this way creates the means for fault diagnosis and detection. We detail the control, interconnection communication infrastructure, instruction distribution, and results processing policies required for our scheme.To determine the effectiveness of the approach, we evaluate its performance in terms of diagnosis latency and percentage of verified operations on 3 to 8 core processors implemented on 3 to 8 tier 3D-SICs, respectively, by means of simulations. Our experiments indicate that the diagnosis latency ranges from 9 to 5 cycles, for 3 to 8 cores, respectively. For transient fault detection our simulations indicate that 86% to 94% of all executed instructions are verified, for 3 to 8 cores, respectively. When only one of the layers is protected against transient faults the number of verified operations increases to 94% to 99%, for the same simulation conditions. This suggests that, if certain conditions are fulfilled at design time, our approach can completely protect one instruction stream identified as being critical for the application. Our simulations clearly indicate that the proposed scheme has the potential to improve the 3D stacked integrated circuits dependability with no performance overhead and at the expense of little area overhead.

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