Functional test generation for hard to detect stuck-at faults using RTL model checking

Prabhu, M. Santhosh; Abraham, Jacob A.

doi:10.1109/ets.2012.6233016

Cited by 9 publications

(3 citation statements)

References 16 publications

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“…Nevertheless, with reduced effort a test engineer can extend and port the existing tests and merely develop additional tests for the remaining, not yet-covered C and F extensions supported by the RI5CY core. Although porting is possible, the reader should note that even though the two systems implement the same ISA extensions, hard-to-test faults are architecture-dependent [23]. The architecture dependency of hard-to-test faults implies a high complexity for test generation.…”

Section: A Risc-v and Functional Test Developmentmentioning

confidence: 99%

A Survey of Recent Developments in Testability, Safety and Security of RISC-V Processors

Anders,

Andreu,

Becker

et al. 2023

2023 IEEE European Test Symposium (ETS)

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With the continued success of the open RISC-V architecture, practical deployment of RISC-V processors necessitates an in-depth consideration of their testability, safety and security aspects. This survey provides an overview of recent developments in this quickly-evolving field. We start with discussing the application of state-of-the-art functional and system-level test solutions to RISC-V processors. Then, we discuss the use of RISC-V processors for safety-related applications; to this end, we outline the essential techniques necessary to obtain safety both in the functional and in the timing domain and review recent processor designs with safety features. Finally, we survey the different aspects of security with respect to RISC-V implementations and discuss the relationship between cryptographic protocols and primitives on the one hand and the RISC-V processor architecture and hardware implementation on the other. We also comment on the role of a RISC-V processor for system security and its resilience against side-channel attacks.

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Section: A Risc-v and Functional Test Developmentmentioning

confidence: 99%

A Survey of Recent Developments in Testability, Safety and Security of RISC-V Processors

Anders,

Andreu,

Becker

et al. 2023

2023 IEEE European Test Symposium (ETS)

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“…Pradhu et al [64] map the gate level stuck-at fault to RTL and build an equivalent faulty RTL model. The fault activation and propagation constraints are captured using control and data flow graph of RTL as an liner temporal logic (LTL) property.…”

Section: Ravi Et Al Show An Rtl To Gate Level Correspondence Inmentioning

confidence: 99%

A Novel RTL ATPG Model Based on Gate Inherent Faults (GIF-PO) of Complex Gates

Strauch¹

2016

Preprint

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This paper starts with a comprehensive survey on RTL ATPG. It then proposes a novel RTL ATPG model based on "Gate Inherent Faults" (GIF). These GIF are extracted from each complex gate (adder, case-statement, etc.) of the RTL source code individually. They are related to the internal logic paths of a complex gate. They are not related to any net/signal in the RTL design. It is observed, that when all GIF on RTL are covered (100%) and the same stimulus is applied, then all gate level stuck-at faults of the netlist are covered (100%) as well. The proposed RTL ATPG model is therefore synthesis independent. This is shown on ITC'99 testcases. The applied semi-automatic test pattern generation process is based on functional simulation.

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“…However the ATPGs employed at the gate level incur higher cost and design complexity. Many hierarchical test generations at the RTL have been proposed in [6], [7], [8], [9], [10], [11], [12], [13], [14], [15], [16] and overcome the issues at the gate level test generation.…”

Section: Introductionmentioning

confidence: 99%

Beyond test pattern generation: Coverage analysis

Bhowmik

Deka

Biswas

2015

2015 International Conference on Industrial Instrumentation and Control (ICIC)

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The size and complexity of the very large scale integrated circuits are ever increasing because of rapid advancements of deep-submicron and nanometer technologies. It has become imperative to address and attack the problems associated with verification at earlier design stages. The paper proposes a high level design verification scheme for the circuits designed at the behavioral level. The scheme is based on selection of a goal node in a control flow graph representation of a design under test. The scheme focuses on generation of suitable test patterns that adds gaining confidence in correctness of the design via code coverage metrics. The scheme does complete verification for a design in two attempts. First time verification attempts testing that exercises a set of test patterns to ensure the correctness. Second time verification involves code coverage analysis with the generated test patterns that accounts amount of correctness of the design. Experiments have been accomplished on a number of custombuilt as well as ITC'99 benchmark circuits and establish the scalability of the proposed scheme. Experimental results establish the fact that high code coverage guarantees quality circuit design.

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Functional test generation for hard to detect stuck-at faults using RTL model checking

Cited by 9 publications

References 16 publications

A Survey of Recent Developments in Testability, Safety and Security of RISC-V Processors

A Survey of Recent Developments in Testability, Safety and Security of RISC-V Processors

A Novel RTL ATPG Model Based on Gate Inherent Faults (GIF-PO) of Complex Gates

Beyond test pattern generation: Coverage analysis

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