Functional Decomposition with Applications to FPGA Synthesis

Scholl, Christoph

doi:10.1007/978-1-4757-3393-8

Cited by 108 publications

(79 citation statements)

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“…Traditional algorithms [3,5,[8][9][10]17] of bi-decomposition are based on BDDs. BDD-based function decomposition approaches implement different forms of bidecomposition, including OR, AND, XOR, MIN and MAX [7,8], targeting optimization of timing [36] and area of the synthesized circuits [9,10].…”

Section: Bdd-based Bi-decompositionmentioning

confidence: 99%

“…, g m are simpler subfunctions. Functional decomposition plays an important role in Electronic Design Automation (EDA) for VLSI, including multi-level logic synthesis and FPGA synthesis [3][4][5].…”

Section: Introductionmentioning

confidence: 99%

“…The general case of bi-decomposing of Boolean network was proposed in [16]. Traditional algorithms [3,5,[8][9][10]17] use BDDs as the underlying data structure. However, BDDs impose severe constraints on the number of input variables circuits can have.…”

Section: Introductionmentioning

confidence: 99%

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Improvements to Satisfiability-Based Boolean Function Bi-Decomposition

Chen

Marques-Silva

2012

VLSI-SoC: Advanced Research for Systems on Chip

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Abstract. Boolean function bi-decomposition is pervasive in logic synthesis. Bi-decomposition entails the decomposition of a Boolean function into two other functions connected by a simple two-input gate. Existing solutions are based on Binary Decision Diagrams (BDDs) and, more recently, on Boolean Satisfiability (SAT). Recent work exploited the identification of Minimally Unsatisfiable Subformulas (MUSes) for computing the sets of variables to use in Boolean function bi-decomposition. This paper develops new techniques for improving the use of MUSes in function bi-decomposition. The first technique exploits structural properties of the function being decomposed, whereas the second technique exploits group-oriented MUSes. Experimental results obtained on representative benchmarks from logic synthesis demonstrate significant improvements both in performance and in the quality of decompositions.

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Section: Bdd-based Bi-decompositionmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

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Improvements to Satisfiability-Based Boolean Function Bi-Decomposition

Chen

Marques-Silva

2012

VLSI-SoC: Advanced Research for Systems on Chip

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“…As a result of all these advantages, the BDD has been often used in tools that supported the process of synthesis such as the BDS (Yang and Ciesielski, 2002), the DDBDD (Cheng et al, 2007), and dekBDD (Opara and Kania, 2010). The essence of using BDDs in the process of synthesis dedicated to FPGA structures has been presented by Scholl (2001). In a BDS PGA system using BDDs, resynthesis occurs (Vemuri et al, 2002).…”

Section: Introductionmentioning

confidence: 99%

Area–Oriented Technology Mapping for LUT–Based Logic Blocks

Kubica

Kania

2017

International Journal of Applied Mathematics and Computer Science

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One of the main aspects of logic synthesis dedicated to FPGA is the problem of technology mapping, which is directly associated with the logic decomposition technique. This paper focuses on using configurable properties of CLBs in the process of logic decomposition and technology mapping. A novel theory and a set of efficient techniques for logic decomposition based on a BDD are proposed. The paper shows that logic optimization can be efficiently carried out by using multiple decomposition. The essence of the proposed synthesis method is multiple cutting of a BDD. A new diagram form called an SMTBDD is proposed. Moreover, techniques that allow finding the best technology mapping oriented to configurability of CLBs are presented. In the experimental section, the presented method (MultiDec) is compared with academic and commercial tools. The experimental results show that the proposed technology mapping strategy leads to good results in terms of the number of CLBs.

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“…This model is the foundation of complex decomposition algorithms dedicated for the LUT-based FPGA (Burns et al, 1998;Lai et al, 1994;Lai et al, 1996;Nowicka et al, 1997;Rawski et al, 2008;Scholl, 2001). The essential parts of synthesis are the partitioning and mapping of a designed circuit into a configurable logic block.…”

mentioning

confidence: 99%

Decomposition-based logic synthesis for PAL-based CPLDs

Opara¹,

Kania²

2010

International Journal of Applied Mathematics and Computer Science

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The paper presents one concept of decomposition methods dedicated to PAL-based CPLDs. The proposed approach is an alternative to the classical one, which is based on two-level minimization of separate single-output functions. The key idea of the algorithm is to search for free blocks that could be implemented in PAL-based logic blocks containing a limited number of product terms. In order to better exploit the number of product terms, two-stage decomposition and BDD-based decomposition are to be used. In BDD-based decomposition methods, functions are represented by Reduced Ordered Binary Decision Diagrams (ROBDDs). The results of experiments prove that the proposed solution is more effective, in terms of the usage of programmable device resources, compared with the classical ones.

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Functional Decomposition with Applications to FPGA Synthesis

Cited by 108 publications

References 0 publications

Improvements to Satisfiability-Based Boolean Function Bi-Decomposition

Improvements to Satisfiability-Based Boolean Function Bi-Decomposition

Area–Oriented Technology Mapping for LUT–Based Logic Blocks

Decomposition-based logic synthesis for PAL-based CPLDs

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